--*/\r
\r
#include "CpuDxe.h"\r
-//FIXME: Remove this ARMv7 specific header\r
-#include <Chipset/ArmV7.h>\r
\r
// First Level Descriptors\r
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
- if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {\r
- // map to strongly ordered\r
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
- } else {\r
- // map to normal non-cachable\r
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
- }\r
+ // map to strongly ordered\r
+ EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
return EFI_UNSUPPORTED;\r
}\r
\r
- // obtain page table base\r
+ // Obtain page table base\r
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
- // calculate number of 4KB page table entries to change\r
+ // Calculate number of 4KB page table entries to change\r
NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
\r
- // iterate for the number of 4KB pages to change\r
+ // Iterate for the number of 4KB pages to change\r
Offset = 0;\r
- for(p=0; p<NumPageEntries; p++) {\r
- // calculate index into first level translation table for page table value\r
+ for(p = 0; p < NumPageEntries; p++) {\r
+ // Calculate index into first level translation table for page table value\r
\r
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
- // read the descriptor from the first level page table\r
+ // Read the descriptor from the first level page table\r
Descriptor = FirstLevelTable[FirstLevelIdx];\r
\r
- // does this descriptor need to be converted from section entry to 4K pages?\r
+ // Does this descriptor need to be converted from section entry to 4K pages?\r
if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
if (EFI_ERROR(Status)) {\r
- // exit for loop\r
+ // Exit for loop\r
break; \r
} \r
\r
- // re-read descriptor\r
+ // Re-read descriptor\r
Descriptor = FirstLevelTable[FirstLevelIdx];\r
}\r
\r
- // obtain page table base address\r
+ // Obtain page table base address\r
PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r
\r
- // calculate index into the page table\r
+ // Calculate index into the page table\r
PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
\r
- // get the entry\r
+ // Get the entry\r
CurrentPageTableEntry = PageTable[PageTableIndex];\r
\r
- // mask off appropriate fields\r
+ // Mask off appropriate fields\r
PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
\r
- // mask in new attributes and/or permissions\r
+ // Mask in new attributes and/or permissions\r
PageTableEntry |= EntryValue;\r
\r
if (VirtualMask != 0) {\r
Status = EFI_SUCCESS;\r
Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
\r
- } // end first level translation table loop\r
+ } // End first level translation table loop\r
\r
return Status;\r
}\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
- if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {\r
- // map to strongly ordered\r
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
- } else {\r
- // map to normal non-cachable\r
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
- }\r
+ // map to strongly ordered\r
+ EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
\r
DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
\r
- // obtain page table base\r
+ // Obtain page table base\r
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
- // calculate index into first level translation table for start of modification\r
+ // Calculate index into first level translation table for start of modification\r
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
- // get section attributes and convert to page attributes\r
+ // Get section attributes and convert to page attributes\r
SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);\r
PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);\r
PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);\r
\r
- // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
+ // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r
if (EFI_ERROR(Status)) {\r
return Status;\r
\r
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
\r
- // write the page table entries out\r
+ // Write the page table entries out\r
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
}\r
\r
- // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
+ // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);\r
\r
- // formulate page table entry, Domain=0, NS=0\r
+ // Formulate page table entry, Domain=0, NS=0\r
PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
\r
- // write the page table entry out, repalcing section entry\r
+ // Write the page table entry out, replacing section entry\r
FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r
\r
return EFI_SUCCESS;\r
EFI_STATUS Status;\r
\r
if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
- // is the base and length a multiple of 1 MB?\r
+ // Is the base and length a multiple of 1 MB?\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
} else {\r
- // base and/or length is not a multiple of 1 MB\r
+ // Base and/or length is not a multiple of 1 MB\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
}\r
\r
- // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
+ // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
// flush and invalidate pages\r
+ //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?\r
ArmCleanInvalidateDataCache ();\r
- \r
+\r
ArmInvalidateInstructionCache ();\r
\r
- // invalidate all TLB entries so changes are synced\r
- ArmInvalidateTlb (); \r
+ // Invalidate all TLB entries so changes are synced\r
+ ArmInvalidateTlb ();\r
\r
return Status;\r
}\r
projects / mirror_edk2.git / blobdiff