/*++\r
\r
-Copyright (c) 2009, Hewlett-Packard Company \r
-Portions copyright (c) 2010, Apple Inc. All rights reserved.\r
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
\r
-All rights reserved. This program and the accompanying materials \r
+This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
\r
#include "CpuDxe.h"\r
\r
-\r
-//\r
-// Translation/page table definitions\r
-//\r
-\r
// First Level Descriptors\r
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r
\r
-// memory space covered by a first level descriptor\r
-#define ARM_PAGE_DESC_ENTRY_MVA_SIZE 0x00100000 // 1MB\r
-\r
-// number of first level descriptors to cover entire 32-bit memory space\r
-#define FIRST_LEVEL_ENTRY_COUNT (0xFFFFFFFF / ARM_PAGE_DESC_ENTRY_MVA_SIZE + 1)\r
-\r
-\r
-// page table 1st level descriptor entries\r
-#define ARM_PAGE_DESC_BASE_MASK 0xFFFFFC00\r
-#define ARM_PAGE_DESC_BASE_SHFIT 10\r
-#define ARM_PAGE_DESC_DOMAIN_MASK 0x000001E0\r
-#define ARM_PAGE_DESC_DOMAIN_SHIFT 5\r
-#define ARM_PAGE_DESC_NS 0x00000008\r
-\r
-#define ARM_FIRST_LEVEL_DESC_ALIGN 0x00004000 // 16KB\r
-\r
-// section 1st level desriptor entries\r
-#define ARM_SECTION_BASE_MASK 0xFFF00000\r
-#define ARM_SECTION_BASE_SHIFT 20\r
-#define ARM_SECTION_NS 0x00080000\r
-#define ARM_SECTION_nG 0x00020000\r
-#define ARM_SECTION_S 0x00010000\r
-#define ARM_SECTION_AP2 0x00008000\r
-#define ARM_SECTION_TEX_MASK 0x00007000\r
-#define ARM_SECTION_TEX_SHIFT 12\r
-#define ARM_SECTION_AP10_MASK 0x00000C00\r
-#define ARM_SECTION_AP10_SHIFT 10\r
-#define ARM_SECTION_DOMAIN_MASK 0x000001E0\r
-#define ARM_SECTION_DOMAIN_SHIFT 5\r
-#define ARM_SECTION_XN 0x00000010\r
-#define ARM_SECTION_C 0x00000008\r
-#define ARM_SECTION_B 0x00000004\r
-\r
-// section level AP[2:0] definitions\r
-#define ARM_SECTION_AP_NO_ACCESS 0 // AP[2:0] = 0\r
-#define ARM_SECTION_AP_READ_WRITE ARM_SECTION_AP10_MASK // AP[2:0] = 011\r
-#define ARM_SECTION_AP_READ_ONLY (ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK) // AP[2:0] = 111\r
-\r
-// common 1st level descriptor fields\r
-#define ARM_DESC_TYPE_MASK 0x00000003\r
-\r
-// descriptor type values\r
-#define ARM_DESC_TYPE_FAULT 0x0\r
-#define ARM_DESC_TYPE_PAGE_TABLE 0x1\r
-#define ARM_DESC_TYPE_SECTION 0x2\r
-\r
-\r
// Second Level Descriptors\r
typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r
\r
-// small page 2nd level descriptor entries\r
-#define ARM_SMALL_PAGE_BASE_MASK 0xFFFFF000\r
-#define ARM_SMALL_PAGE_INDEX_MASK 0x000FF000\r
-#define ARM_SMALL_PAGE_BASE_SHIFT 12\r
-#define ARM_SMALL_PAGE_TEX_MASK 0x000001C0\r
-#define ARM_SMALL_PAGE_TEX_SHIFT 6\r
-#define ARM_SMALL_PAGE_XN 0x00000001\r
-\r
-// large page 2nd level descriptor entries\r
-#define ARM_LARGE_PAGE_BASE_MASK 0xFFFF0000\r
-#define ARM_LARGE_PAGE_BASE_SHIFT 16\r
-#define ARM_LARGE_PAGE_TEX_MASK 0x00007000\r
-#define ARM_LARGE_PAGE_TEX_SHIFT 12\r
-#define ARM_LARGE_PAGE_XN 0x00008000\r
-\r
-// common 2nd level desriptor fields\r
-#define ARM_PAGE_nG 0x00000800\r
-#define ARM_PAGE_S 0x00000400\r
-#define ARM_PAGE_AP2 0x00000200\r
-#define ARM_PAGE_AP10_MASK 0x00000030\r
-#define ARM_PAGE_AP10_SHIFT 4\r
-#define ARM_PAGE_C 0x00000008\r
-#define ARM_PAGE_B 0x00000004\r
-#define ARM_PAGE_DESC_TYPE_MASK 0x00000003\r
-\r
-// descriptor type values\r
-#define ARM_PAGE_TYPE_FAULT 0x0\r
-#define ARM_PAGE_TYPE_LARGE 0x1\r
-#define ARM_PAGE_TYPE_SMALL 0x2\r
-#define ARM_PAGE_TYPE_SMALL_XN 0x3\r
-\r
-#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / SIZE_4KB)\r
-\r
-\r
-// Translation Table Base 0 fields\r
-#define ARM_TTBR0_BASE_MASK 0xFFFFC000\r
-#define ARM_TTBR0_BASE_SHIFT 14\r
-#define ARM_TTRB0_NOS 0x00000020\r
-\r
-// define the combination of interesting attributes: cacheability and access permissions\r
-#define ARM_SECTION_CACHEABILITY_MASK ( ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B )\r
-#define ARM_SECTION_RW_PERMISSIONS_MASK ( ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK )\r
-#define ARM_DESCRIPTOR_ATTRIBUTES ( ARM_SECTION_CACHEABILITY_MASK | ARM_SECTION_RW_PERMISSIONS_MASK | ARM_SECTION_XN )\r
-\r
-// cacheability values for section entries\r
-#define ARM_SECTION_STRONGLY_ORDERED 0\r
-#define ARM_SECTION_SHAREABLE_DEVICE ARM_SECTION_B\r
-#define ARM_SECTION_WRITE_THROUGH ARM_SECTION_C\r
-#define ARM_SECTION_WRITE_BACK_NWA ( ARM_SECTION_C| ARM_SECTION_B )\r
-#define ARM_SECTION_NORMAL_UNCACHEABLE ( 0x1 << ARM_SECTION_TEX_SHIFT )\r
-#define ARM_SECTION_WRITE_BACK ( ( 0x1 << ARM_SECTION_TEX_SHIFT ) | ARM_SECTION_C | ARM_SECTION_B )\r
-#define ARM_SECTION_NONSHAREABLE_DEVICE ( 0x2 << ARM_SECTION_TEX_SHIFT )\r
-\r
-// permissions values for section entries\r
-#define ARM_SECTION_NO_ACCESS 0\r
-#define ARM_SECTION_PRIV_ACCESS_ONLY ( 0x1 << ARM_SECTION_AP10_SHIFT)\r
-#define ARM_SECTION_USER_READ_ONLY ( 0x2 << ARM_SECTION_AP10_SHIFT)\r
-#define ARM_SECTION_FULL_ACCESS ( 0x3 << ARM_SECTION_AP10_SHIFT)\r
-#define ARM_SECTION_PRIV_READ_ONLY ( ARM_SECTION_AP2 | (0x1 << ARM_SECTION_AP10_SHIFT) )\r
-#define ARM_SECTION_READ_ONLY_DEP ( ARM_SECTION_AP2 | (0x2 << ARM_SECTION_AP10_SHIFT) )\r
-#define ARM_SECTION_READ_ONLY ( ARM_SECTION_AP2 | (0x3 << ARM_SECTION_AP10_SHIFT) )\r
-\r
-\r
-\r
EFI_STATUS \r
SectionToGcdAttributes (\r
IN UINT32 SectionAttributes,\r
*GcdAttributes = 0;\r
\r
// determine cacheability attributes\r
- switch(SectionAttributes & ARM_SECTION_CACHEABILITY_MASK) {\r
- case ARM_SECTION_STRONGLY_ORDERED:\r
+ switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {\r
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:\r
*GcdAttributes |= EFI_MEMORY_UC;\r
break;\r
- case ARM_SECTION_SHAREABLE_DEVICE:\r
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:\r
*GcdAttributes |= EFI_MEMORY_UC;\r
break;\r
- case ARM_SECTION_WRITE_THROUGH:\r
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r
*GcdAttributes |= EFI_MEMORY_WT;\r
break;\r
- case ARM_SECTION_WRITE_BACK_NWA:\r
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r
*GcdAttributes |= EFI_MEMORY_WB;\r
break;\r
- case ARM_SECTION_NORMAL_UNCACHEABLE:\r
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:\r
*GcdAttributes |= EFI_MEMORY_WC;\r
break;\r
- case ARM_SECTION_WRITE_BACK:\r
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:\r
*GcdAttributes |= EFI_MEMORY_WB;\r
break;\r
- case ARM_SECTION_NONSHAREABLE_DEVICE:\r
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r
*GcdAttributes |= EFI_MEMORY_UC;\r
break;\r
default:\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
// determine protection attributes\r
- switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {\r
- case ARM_SECTION_NO_ACCESS: // no read, no write\r
+ switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {\r
+ case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write\r
//*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
break;\r
\r
- case ARM_SECTION_PRIV_ACCESS_ONLY:\r
- case ARM_SECTION_FULL_ACCESS:\r
+ case TT_DESCRIPTOR_SECTION_AP_RW_NO:\r
+ case TT_DESCRIPTOR_SECTION_AP_RW_RW:\r
// normal read/write access, do not add additional attributes\r
break;\r
\r
// read only cases map to write-protect\r
- case ARM_SECTION_PRIV_READ_ONLY:\r
- case ARM_SECTION_READ_ONLY_DEP:\r
- case ARM_SECTION_READ_ONLY:\r
+ case TT_DESCRIPTOR_SECTION_AP_RO_NO:\r
+ case TT_DESCRIPTOR_SECTION_AP_RO_RO:\r
*GcdAttributes |= EFI_MEMORY_WP;\r
break;\r
\r
}\r
\r
// now process eXectue Never attribute\r
- if ((SectionAttributes & ARM_SECTION_XN) != 0 ) {\r
+ if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {\r
+ *GcdAttributes |= EFI_MEMORY_XP;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+PageToGcdAttributes (\r
+ IN UINT32 PageAttributes,\r
+ OUT UINT64 *GcdAttributes\r
+ )\r
+{\r
+ *GcdAttributes = 0;\r
+\r
+ // determine cacheability attributes\r
+ switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {\r
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:\r
+ *GcdAttributes |= EFI_MEMORY_UC;\r
+ break;\r
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE:\r
+ *GcdAttributes |= EFI_MEMORY_UC;\r
+ break;\r
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r
+ *GcdAttributes |= EFI_MEMORY_WT;\r
+ break;\r
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r
+ *GcdAttributes |= EFI_MEMORY_WB;\r
+ break;\r
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE:\r
+ *GcdAttributes |= EFI_MEMORY_WC;\r
+ break;\r
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC:\r
+ *GcdAttributes |= EFI_MEMORY_WB;\r
+ break;\r
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r
+ *GcdAttributes |= EFI_MEMORY_UC;\r
+ break;\r
+ default:\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ // determine protection attributes\r
+ switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {\r
+ case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write\r
+ //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
+ break;\r
+\r
+ case TT_DESCRIPTOR_PAGE_AP_RW_NO:\r
+ case TT_DESCRIPTOR_PAGE_AP_RW_RW:\r
+ // normal read/write access, do not add additional attributes\r
+ break;\r
+\r
+ // read only cases map to write-protect\r
+ case TT_DESCRIPTOR_PAGE_AP_RO_NO:\r
+ case TT_DESCRIPTOR_PAGE_AP_RO_RO:\r
+ *GcdAttributes |= EFI_MEMORY_WP;\r
+ break;\r
+\r
+ default:\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ // now process eXectue Never attribute\r
+ if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {\r
*GcdAttributes |= EFI_MEMORY_XP;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
+EFI_STATUS\r
+SyncCacheConfigPage (\r
+ IN UINT32 SectionIndex,\r
+ IN UINT32 FirstLevelDescriptor,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,\r
+ IN OUT UINT64 *NextRegionLength,\r
+ IN OUT UINT32 *NextSectionAttributes\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT32 i;\r
+ volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;\r
+ UINT32 NextPageAttributes = 0;\r
+ UINT32 PageAttributes = 0;\r
+ UINT32 BaseAddress;\r
+ UINT64 GcdAttributes;\r
+\r
+ // Get the Base Address from FirstLevelDescriptor;\r
+ BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+\r
+ // Convert SectionAttributes into PageAttributes\r
+ NextPageAttributes =\r
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |\r
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);\r
+\r
+ // obtain page table base\r
+ SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
+\r
+ for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {\r
+ if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {\r
+ // extract attributes (cacheability and permissions)\r
+ PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);\r
+\r
+ if (NextPageAttributes == 0) {\r
+ // start on a new region\r
+ *NextRegionLength = 0;\r
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
+ NextPageAttributes = PageAttributes;\r
+ } else if (PageAttributes != NextPageAttributes) {\r
+ // Convert Section Attributes into GCD Attributes\r
+ Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
+\r
+ // start on a new region\r
+ *NextRegionLength = 0;\r
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
+ NextPageAttributes = PageAttributes;\r
+ }\r
+ } else if (NextPageAttributes != 0) {\r
+ // Convert Page Attributes into GCD Attributes\r
+ Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
+\r
+ *NextRegionLength = 0;\r
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
+ NextPageAttributes = 0;\r
+ }\r
+ *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;\r
+ }\r
+\r
+ // Convert back PageAttributes into SectionAttributes\r
+ *NextSectionAttributes =\r
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |\r
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
\r
EFI_STATUS\r
SyncCacheConfig (\r
{\r
EFI_STATUS Status;\r
UINT32 i;\r
- UINT32 Descriptor;\r
- UINT32 SectionAttributes;\r
EFI_PHYSICAL_ADDRESS NextRegionBase;\r
UINT64 NextRegionLength;\r
+ UINT32 NextSectionAttributes = 0;\r
+ UINT32 SectionAttributes = 0;\r
UINT64 GcdAttributes;\r
- UINT32 NextRegionAttributes = 0;\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
UINTN NumberOfDescriptors;\r
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
// with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r
\r
// obtain page table base\r
- FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTranslationTableBaseAddress ());\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());\r
\r
+ // Get the first region\r
+ NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r
\r
// iterate through each 1MB descriptor\r
NextRegionBase = NextRegionLength = 0;\r
- for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {\r
-\r
- // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section\r
- Descriptor = FirstLevelTable[i] | (ARM_SECTION_BASE_MASK & (i << ARM_SECTION_BASE_SHIFT));\r
-\r
- // extract attributes (cacheability and permissions)\r
- SectionAttributes = Descriptor & 0xDEC;\r
-\r
- // do we already have an existing region (or are we about to finish)?\r
- // Skip the first entry, and make sure we close on the last entry\r
- if ( (NextRegionLength > 0) || (i == (FIRST_LEVEL_ENTRY_COUNT-1)) ) {\r
- // attributes are changing, update attributes in GCD\r
- if (SectionAttributes != NextRegionAttributes) {\r
- \r
- // convert section entry attributes to GCD bitmask\r
- Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r
+ for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {\r
+ if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
+ // extract attributes (cacheability and permissions)\r
+ SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r
+\r
+ if (NextSectionAttributes == 0) {\r
+ // start on a new region\r
+ NextRegionLength = 0;\r
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ NextSectionAttributes = SectionAttributes;\r
+ } else if (SectionAttributes != NextSectionAttributes) {\r
+ // Convert Section Attributes into GCD Attributes\r
+ Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
ASSERT_EFI_ERROR (Status);\r
\r
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
\r
-\r
// start on a new region\r
NextRegionLength = 0;\r
- NextRegionBase = Descriptor & ARM_SECTION_BASE_MASK;\r
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ NextSectionAttributes = SectionAttributes;\r
}\r
- }\r
+ NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
+ } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {\r
+ Status = SyncCacheConfigPage (\r
+ i,FirstLevelTable[i],\r
+ NumberOfDescriptors, MemorySpaceMap,\r
+ &NextRegionBase,&NextRegionLength,&NextSectionAttributes);\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else {\r
+ // We do not support yet 16MB sections\r
+ ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION);\r
\r
- // starting a new region?\r
- if (NextRegionLength == 0) {\r
- NextRegionAttributes = SectionAttributes;\r
- }\r
+ // start on a new region\r
+ if (NextSectionAttributes != 0) {\r
+ // Convert Section Attributes into GCD Attributes\r
+ Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
+ ASSERT_EFI_ERROR (Status);\r
\r
- NextRegionLength += ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
\r
+ NextRegionLength = 0;\r
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ NextSectionAttributes = 0;\r
+ }\r
+ NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
+ }\r
} // section entry loop\r
\r
+ if (NextSectionAttributes != 0) {\r
+ // Convert Section Attributes into GCD Attributes\r
+ Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
+ }\r
+\r
return EFI_SUCCESS;\r
}\r
\r
\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
// EntryValue: values at bit positions specified by EntryMask\r
- EntryMask = ARM_PAGE_DESC_TYPE_MASK;\r
- EntryValue = ARM_PAGE_TYPE_SMALL;\r
+ EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;\r
+ EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
// Although the PI spec is unclear on this the GCD guarantees that only\r
// one Attribute bit is set at a time, so we can safely use a switch statement\r
switch (Attributes) {\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// map to strongly ordered\r
- EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
+ EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// map to normal non-cachable\r
- EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+ EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
break;\r
\r
case EFI_MEMORY_WT:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// write through with no-allocate\r
- EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
+ EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
break;\r
\r
case EFI_MEMORY_WB:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// write back (with allocate)\r
- EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
+ EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
break;\r
\r
case EFI_MEMORY_WP:\r
case EFI_MEMORY_UCE:\r
// cannot be implemented UEFI definition unclear for ARM\r
// Cause a page fault if these ranges are accessed.\r
- EntryValue = ARM_PAGE_TYPE_FAULT;\r
+ EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
break;\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
- // obtain page table base\r
- FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
+ // Obtain page table base\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
- // calculate number of 4KB page table entries to change\r
- NumPageEntries = Length/SIZE_4KB;\r
+ // Calculate number of 4KB page table entries to change\r
+ NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
\r
- // iterate for the number of 4KB pages to change\r
+ // Iterate for the number of 4KB pages to change\r
Offset = 0;\r
- for(p=0; p<NumPageEntries; p++) {\r
- // calculate index into first level translation table for page table value\r
+ for(p = 0; p < NumPageEntries; p++) {\r
+ // Calculate index into first level translation table for page table value\r
\r
- FirstLevelIdx = ((BaseAddress + Offset) & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
- ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+ ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
- // read the descriptor from the first level page table\r
+ // Read the descriptor from the first level page table\r
Descriptor = FirstLevelTable[FirstLevelIdx];\r
\r
- // does this descriptor need to be converted from section entry to 4K pages?\r
- if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
- Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);\r
+ // Does this descriptor need to be converted from section entry to 4K pages?\r
+ if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r
+ Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
if (EFI_ERROR(Status)) {\r
- // exit for loop\r
+ // Exit for loop\r
break; \r
} \r
\r
- // re-read descriptor\r
+ // Re-read descriptor\r
Descriptor = FirstLevelTable[FirstLevelIdx];\r
}\r
\r
- // obtain page table base address\r
- PageTable = (ARM_PAGE_TABLE_ENTRY *)(Descriptor & ARM_SMALL_PAGE_BASE_MASK);\r
+ // Obtain page table base address\r
+ PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r
\r
- // calculate index into the page table\r
- PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;\r
- ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
+ // Calculate index into the page table\r
+ PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
+ ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
\r
- // get the entry\r
+ // Get the entry\r
CurrentPageTableEntry = PageTable[PageTableIndex];\r
\r
- // mask off appropriate fields\r
+ // Mask off appropriate fields\r
PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
\r
- // mask in new attributes and/or permissions\r
+ // Mask in new attributes and/or permissions\r
PageTableEntry |= EntryValue;\r
\r
if (VirtualMask != 0) {\r
}\r
\r
if (CurrentPageTableEntry != PageTableEntry) {\r
- Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << ARM_SECTION_BASE_SHIFT) + (PageTableIndex << ARM_SMALL_PAGE_BASE_SHIFT));\r
- if ((CurrentPageTableEntry & ARM_PAGE_C) == ARM_PAGE_C) {\r
+ Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
+ if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {\r
// The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r
// Note assumes switch(Attributes), not ARMv7 possibilities\r
- WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);\r
+ WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r
}\r
\r
// Only need to update if we are changing the entry \r
}\r
\r
Status = EFI_SUCCESS;\r
- Offset += SIZE_4KB;\r
+ Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
\r
- } // end first level translation table loop\r
+ } // End first level translation table loop\r
\r
return Status;\r
}\r
// EntryValue: values at bit positions specified by EntryMask\r
\r
// Make sure we handle a section range that is unmapped \r
- EntryMask = ARM_DESC_TYPE_MASK;\r
- EntryValue = ARM_DESC_TYPE_SECTION;\r
+ EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;\r
+ EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;\r
\r
// Although the PI spec is unclear on this the GCD guarantees that only\r
// one Attribute bit is set at a time, so we can safely use a switch statement\r
switch(Attributes) {\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
+ EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// map to strongly ordered\r
- EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
+ EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
+ EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// map to normal non-cachable\r
- EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+ EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
break;\r
\r
case EFI_MEMORY_WT:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
+ EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// write through with no-allocate\r
- EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
+ EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
break;\r
\r
case EFI_MEMORY_WB:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
+ EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// write back (with allocate)\r
- EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
+ EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
break;\r
\r
case EFI_MEMORY_WP:\r
case EFI_MEMORY_UCE:\r
// cannot be implemented UEFI definition unclear for ARM\r
// Cause a page fault if these ranges are accessed.\r
- EntryValue = ARM_DESC_TYPE_FAULT;\r
+ EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
break;\r
\r
}\r
\r
// obtain page table base\r
- FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
// calculate index into first level translation table for start of modification\r
- FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
- ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+ ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
// calculate number of 1MB first level entries this applies to\r
- NumSections = Length / ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r
+ NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;\r
\r
// iterate through each descriptor\r
for(i=0; i<NumSections; i++) {\r
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
\r
// has this descriptor already been coverted to pages?\r
- if ((CurrentDescriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r
// forward this 1MB range to page table function instead\r
- Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
+ Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);\r
} else {\r
// still a section entry\r
\r
}\r
\r
if (CurrentDescriptor != Descriptor) {\r
- Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << ARM_SECTION_BASE_SHIFT);\r
- if ((CurrentDescriptor & ARM_SECTION_C) == ARM_SECTION_C) {\r
+ Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {\r
// The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r
// Note assumes switch(Attributes), not ARMv7 possabilities\r
WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
UINT32 SectionDescriptor;\r
UINT32 PageTableDescriptor;\r
UINT32 PageDescriptor;\r
- UINT32 i;\r
+ UINT32 Index;\r
\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
\r
DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
\r
- // obtain page table base\r
- FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
+ // Obtain page table base\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
- // calculate index into first level translation table for start of modification\r
- FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
- ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+ // Calculate index into first level translation table for start of modification\r
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+ ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
- // get section attributes and convert to page attributes\r
+ // Get section attributes and convert to page attributes\r
SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
- PageDescriptor = ARM_PAGE_TYPE_SMALL;\r
- PageDescriptor |= ((SectionDescriptor & ARM_SECTION_TEX_MASK) >> ARM_SECTION_TEX_SHIFT) << ARM_SMALL_PAGE_TEX_SHIFT;\r
- if ((SectionDescriptor & ARM_SECTION_B) != 0) {\r
- PageDescriptor |= ARM_PAGE_B;\r
- }\r
- if ((SectionDescriptor & ARM_SECTION_C) != 0) {\r
- PageDescriptor |= ARM_PAGE_C;\r
- }\r
- PageDescriptor |= ((SectionDescriptor & ARM_SECTION_AP10_MASK) >> ARM_SECTION_AP10_SHIFT) << ARM_PAGE_AP10_SHIFT;\r
- if ((SectionDescriptor & ARM_SECTION_AP2) != 0) {\r
- PageDescriptor |= ARM_PAGE_AP2;\r
- }\r
- if ((SectionDescriptor & ARM_SECTION_XN) != 0) {\r
- PageDescriptor |= ARM_PAGE_TYPE_SMALL_XN;\r
- }\r
- if ((SectionDescriptor & ARM_SECTION_nG) != 0) {\r
- PageDescriptor |= ARM_PAGE_nG;\r
- }\r
- if ((SectionDescriptor & ARM_SECTION_S) != 0) {\r
- PageDescriptor |= ARM_PAGE_S;\r
- }\r
-\r
- // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
+ PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
+ PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);\r
+ PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);\r
+ PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);\r
+ PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);\r
+ PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);\r
+\r
+ // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r
if (EFI_ERROR(Status)) {\r
return Status;\r
\r
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
\r
- // write the page table entries out\r
- for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/SIZE_4KB); i++) {\r
- PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r
+ // Write the page table entries out\r
+ for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
+ PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
}\r
\r
- // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
- WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);\r
+ // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
+ WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);\r
\r
- // formulate page table entry, Domain=0, NS=0\r
- PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r
+ // Formulate page table entry, Domain=0, NS=0\r
+ PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
\r
- // write the page table entry out, repalcing section entry\r
+ // Write the page table entry out, replacing section entry\r
FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r
\r
return EFI_SUCCESS;\r
EFI_STATUS Status;\r
\r
if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
- // is the base and length a multiple of 1 MB?\r
+ // Is the base and length a multiple of 1 MB?\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
} else {\r
- // base and/or length is not a multiple of 1 MB\r
+ // Base and/or length is not a multiple of 1 MB\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
}\r
\r
- // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
+ // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
// flush and invalidate pages\r
+ //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?\r
ArmCleanInvalidateDataCache ();\r
- \r
+\r
ArmInvalidateInstructionCache ();\r
\r
- // invalidate all TLB entries so changes are synced\r
- ArmInvalidateTlb (); \r
+ // Invalidate all TLB entries so changes are synced\r
+ ArmInvalidateTlb ();\r
\r
return Status;\r
}\r
)\r
{\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r
- if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){\r
+ if ( ((BaseAddress & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0) || ((Length & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0)){\r
// minimum granularity is SIZE_4KB (4KB on ARM)\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r
return EFI_UNSUPPORTED;\r
CpuConvertPagesToUncachedVirtualAddress,\r
CpuReconvertPages\r
};\r
-\r
-\r
-\r
-\r
projects / mirror_edk2.git / blobdiff