\r
Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>\r
-Copyright (c) 2011, ARM Limited. All rights reserved.<BR>\r
+Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>\r
\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
SystemMemoryBase, SystemMemoryLength/1024/1024,\r
(CacheAttributes == DDR_ATTRIBUTES_CACHED) ? "cacheable" : "uncacheable"));\r
\r
- ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU (error code: %r)\n", Status));\r
+ }\r
\r
BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
}\r