#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)\r
#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)\r
#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)\r
-#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)\r
+#define DMC_DIRECT_CMD_CHIP_ADDR(n)\s\s\s\s((n & 0x3) << 20)\r
\r
\r
//\r
//\r
\r
if (config->has_qos) {\r
- // CLCD AXIID = 000\r
- DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);\r
-\r
- // Default disable QoS\r
- DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\s// CLCD AXIID = 000\r
+\s\sDmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);\r
+\r
+\s\s// Default disable QoS\r
+\s\sDmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+\s\sDmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
}\r
\r
//\r
// |======================================\r
DmcWriteReg(DMC_MEMORY_CFG3_REG, config->memory_cfg3);\r
\r
- // |========================================================\r
- // |Set Test Chip PHY Registers via PL341 User Config Reg\r
- // |Note that user_cfgX registers are Write Only\r
- // |\r
- // |DLL Freq set = 250MHz - 266MHz\r
- // |======================================================== \r
- DmcWriteReg(DMC_USER_0_CFG_REG, 0x7C924924);\r
+\s\s// |========================================================\r
+\s\s// |Set Test Chip PHY Registers via PL341 User Config Reg\r
+\s\s// |Note that user_cfgX registers are Write Only\r
+\s\s// |\r
+\s\s// |DLL Freq set = 250MHz - 266MHz\r
+\s\s// |======================================================== \r
+\s\sDmcWriteReg(DMC_USER_0_CFG_REG, 0x7C924924);\r
\r
- // user_config2\r
- // ------------\r
- // Set defaults before calibrating the DDR2 buffer impendence\r
- // -Disable ODT\r
- // -Default drive strengths\r
- DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r
+\s\s// user_config2\r
+\s\s// ------------\r
+\s\s// Set defaults before calibrating the DDR2 buffer impendence\r
+\s\s// -Disable ODT\r
+\s\s// -Default drive strengths\r
+\s\sDmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r
\r
- // |=======================================================\r
- // |Auto calibrate the DDR2 buffers impendence \r
- // |=======================================================\r
- val32 = DmcReadReg(DMC_USER_STATUS_REG);\r
- while (!(val32 & 0x100)) {\r
- val32 = DmcReadReg(DMC_USER_STATUS_REG);\r
- }\r
-\r
- // Set the output driven strength\r
- DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | \r
- (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | \r
- (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) |\r
- (0x1 << TC_UIOHOCT_SHIFT) | \r
- (0x1 << TC_UIOHSTOP_SHIFT));\r
-\r
- // |======================================\r
- // | Set PL341 Feature Control Register \r
- // |======================================\r
- // | Disable early BRESP - use to optimise CLCD performance\r
- DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r
+\s\s// |=======================================================\r
+\s\s// |Auto calibrate the DDR2 buffers impendence \r
+\s\s// |=======================================================\r
+\s\sval32 = DmcReadReg(DMC_USER_STATUS_REG);\r
+\s\swhile (!(val32 & 0x100)) {\r
+\s\s val32 = DmcReadReg(DMC_USER_STATUS_REG);\r
+\s\s}\r
+\r
+\s\s// Set the output driven strength\r
+\s\sDmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | \r
+\s\s\s\s (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | \r
+\s\s\s\s (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) |\r
+\s\s\s\s (0x1 << TC_UIOHOCT_SHIFT) | \r
+\s\s\s\s (0x1 << TC_UIOHSTOP_SHIFT));\r
+\r
+\s\s// |======================================\r
+\s\s// | Set PL341 Feature Control Register \r
+\s\s// |======================================\r
+\s\s// | Disable early BRESP - use to optimise CLCD performance\r
+\s\sDmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r
\r
//=================\r
// Config memories\r
//=================\r
\r
for (chip = 0; chip <= config-> max_chip; chip++) {\r
- // send nop\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
- // pre-charge all\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
-\r
- // delay\r
- for (i = 0; i < 10; i++) {\r
- val32 = DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- // set (EMR2) extended mode register 2\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, \r
- DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
- DMC_DIRECT_CMD_BANKADDR(2) | \r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
- // set (EMR3) extended mode register 3\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, \r
- DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
- DMC_DIRECT_CMD_BANKADDR(3) | \r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
-\r
- // =================================\r
- // set (EMR) Extended Mode Register\r
- // ==================================\r
- // Put into OCD default state\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, \r
- DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
- DMC_DIRECT_CMD_BANKADDR(1) | \r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
-\r
- // =========================================================== \r
- // set (MR) mode register - With DLL reset\r
- // ===========================================================\r
- // Burst Length = 4 (010)\r
- // Burst Type = Seq (0)\r
- // Latency = 4 (100)\r
- // Test mode = Off (0)\r
- // DLL reset = Yes (1)\r
- // Wr Recovery = 4 (011) \r
- // PD = Normal (0)\r
+\s\s// send nop\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
+\s\s// pre-charge all\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
+\r
+\s\s// delay\r
+\s\sfor (i = 0; i < 10; i++) {\r
+\s\s val32 = DmcReadReg(DMC_STATUS_REG);\r
+\s\s}\r
+\r
+\s\s// set (EMR2) extended mode register 2\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, \r
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(2) | \r
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\s\s// set (EMR3) extended mode register 3\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, \r
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(3) | \r
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+\s\s// =================================\r
+\s\s// set (EMR) Extended Mode Register\r
+\s\s// ==================================\r
+\s\s// Put into OCD default state\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, \r
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(1) | \r
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+\s\s// =========================================================== \r
+\s\s// set (MR) mode register - With DLL reset\r
+\s\s// ===========================================================\r
+\s\s// Burst Length = 4 (010)\r
+\s\s// Burst Type = Seq (0)\r
+\s\s// Latency = 4 (100)\r
+\s\s// Test mode = Off (0)\r
+\s\s// DLL reset = Yes (1)\r
+\s\s// Wr Recovery = 4 (011) \r
+\s\s// PD = Normal (0)\r
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080742);\r
\r
- // pre-charge all \r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
- // auto-refresh \r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
- // auto-refresh \r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
-\r
- // delay\r
- for (i = 0; i < 10; i++) {\r
- val32 = DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- // =========================================================== \r
- // set (MR) mode register - Without DLL reset\r
- // ===========================================================\r
+\s\s// pre-charge all \r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
+\s\s// auto-refresh \r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
+\s\s// auto-refresh \r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
+\r
+\s\s// delay\r
+\s\sfor (i = 0; i < 10; i++) {\r
+\s\s val32 = DmcReadReg(DMC_STATUS_REG);\r
+\s\s}\r
+\r
+\s\s// =========================================================== \r
+\s\s// set (MR) mode register - Without DLL reset\r
+\s\s// ===========================================================\r
// auto-refresh\r
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080642);\r
val32 = DmcReadReg(DMC_STATUS_REG);\r
}\r
\r
- // ====================================================== \r
- // set (EMR) extended mode register - Enable OCD defaults\r
- // ====================================================== \r
- val32 = 0; //NOP\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |\r
- (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | \r
- DDR_EMR_RTT_75R | \r
- (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));\r
-\r
- // delay\r
- for (i = 0; i < 10; i++) {\r
- val32 = DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- // Set (EMR) extended mode register - OCD Exit\r
- val32 = 0; //NOP\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 | \r
- (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | \r
- DDR_EMR_RTT_75R |\r
- (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));\r
+\s\s// ====================================================== \r
+\s\s// set (EMR) extended mode register - Enable OCD defaults\r
+\s\s// ====================================================== \r
+\s\sval32 = 0; //NOP\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |\r
+\s\s\s\s (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | \r
+\s\s\s\s DDR_EMR_RTT_75R | \r
+\s\s\s\s (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));\r
+\r
+\s\s// delay\r
+\s\sfor (i = 0; i < 10; i++) {\r
+\s\s val32 = DmcReadReg(DMC_STATUS_REG);\r
+\s\s}\r
+\r
+\s\s// Set (EMR) extended mode register - OCD Exit\r
+\s\sval32 = 0; //NOP\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 | \r
+\s\s\s\s (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | \r
+\s\s\s\s DDR_EMR_RTT_75R |\r
+\s\s\s\s (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));\r
\r
}\r
\r
projects / mirror_edk2.git / blobdiff