\r
#include <AsmMacroIoLib.h>\r
#include <Library/PcdLib.h>\r
+#include <Drivers/PL354Smc.h>\r
#include <AutoGen.h>\r
\r
INCLUDE AsmMacroIoLib.inc\r
\r
- EXPORT InitializeSMC\r
+ EXPORT SMCInitializeNOR\r
+ EXPORT SMCInitializeSRAM\r
+ EXPORT SMCInitializePeripherals\r
+ EXPORT SMCInitializeVRAM\r
\r
PRESERVE8\r
AREA ModuleInitializeSMC, CODE, READONLY\r
\r
-// Static memory configuation definitions for SMC\r
-SmcDirectCmd EQU 0x10\r
-SmcSetCycles EQU 0x14\r
-SmcSetOpMode EQU 0x18\r
-\r
// CS0 CS0-Interf0 NOR1 flash on the motherboard\r
// CS1 CS1-Interf0 Reserved for the motherboard\r
// CS2 CS2-Interf0 SRAM on the motherboard\r
// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
\r
// IN r1 SmcBase\r
-// IN r2 VideoSRamBase\r
+// IN r2 ChipSelect\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
// could be overwritten (case of 'r0')\r
-InitializeSMC\r
-//\r
-// Setup NOR1 (CS0-Interface0)\r
-//\r
-\r
- //Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- //Read cycle timeout = 0xA (0:3)\r
- //Write cycle timeout = 0x3(7:4)\r
- //OE Assertion Delay = 0x9(11:8)\r
- //WE Assertion delay = 0x3(15:12)\r
- //Page cycle timeout = 0x2(19:16) \r
+SMCInitializeNOR\r
+ // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
+ // - Read cycle timeout = 0xA (0:3)\r
+ // - Write cycle timeout = 0x3(7:4)\r
+ // - OE Assertion Delay = 0x9(11:8)\r
+ // - WE Assertion delay = 0x3(15:12)\r
+ // - Page cycle timeout = 0x2(19:16)\r
ldr r0, = 0x0002393A\r
- str r0, [r1, #SmcSetCycles]\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
- //Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- // 0x00000002 = MemoryWidth: 32bit\r
- // 0x00000028 = ReadMemoryBurstLength:continuous\r
- // 0x00000280 = WriteMemoryBurstLength:continuous\r
- // 0x00000800 = Set Address Valid\r
- ldr r0, = 0x00000AAA\r
- str r0, [r1, #SmcSetOpMode] \r
-\r
- //Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- // 0x00000000 = ChipSelect0-Interface 0\r
- // 0x00400000 = CmdTypes: UpdateRegs\r
- ldr r0, = 0x00400000\r
- str r0, [r1, #SmcDirectCmd] \r
+ // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
+ ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+\r
+ // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
+ ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
+ orr r0, r0, r2\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
+ bx lr\r
+\r
+\r
//\r
// Setup SRAM (CS2-Interface0)\r
//\r
+SMCInitializeSRAM\r
ldr r0, = 0x00027158\r
- str r0, [r1, #SmcSetCycles]\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
- // 0x00000002 = MemoryWidth: 32bit\r
- // 0x00000800 = Set Address Valid\r
- ldr r0, = 0x00000802\r
- str r0, [r1, #SmcSetOpMode]\r
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
- // 0x01000000 = ChipSelect2-Interface 0\r
- // 0x00400000 = CmdTypes: UpdateRegs\r
- ldr r0, = 0x01400000\r
- str r0, [r1, #SmcDirectCmd]\r
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
+ bx lr\r
\r
+SMCInitializePeripherals\r
//\r
// USB/Eth/VRAM (CS3-Interface0)\r
//\r
ldr r0, = 0x000CD2AA\r
- str r0, [r1, #SmcSetCycles]\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
- // 0x00000002 = MemoryWidth: 32bit\r
- // 0x00000004 = Memory reads are synchronous\r
- // 0x00000040 = Memory writes are synchronous\r
- ldr r0, = 0x00000046\r
- str r0, [r1, #SmcSetOpMode] \r
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
- // 0x01800000 = ChipSelect3-Interface 0\r
- // 0x00400000 = CmdTypes: UpdateRegs\r
- ldr r0, = 0x01C00000\r
- str r0, [r1, #SmcDirectCmd] \r
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
\r
-//\r
-// Setup NOR3 (CS0-Interface1)\r
-//\r
- ldr r0, = 0x0002393A\r
- str r0, [r1, #SmcSetCycles]\r
- \r
- // 0x00000002 = MemoryWidth: 32bit\r
- // 0x00000028 = ReadMemoryBurstLength:continuous\r
- // 0x00000280 = WriteMemoryBurstLength:continuous\r
- // 0x00000800 = Set Address Valid\r
- ldr r0, = 0x00000AAA\r
- str r0, [r1, #SmcSetOpMode] \r
- \r
- // 0x02000000 = ChipSelect0-Interface 1\r
- // 0x00400000 = CmdTypes: UpdateRegs\r
- ldr r0, = 0x02400000\r
- str r0, [r1, #SmcDirectCmd] \r
- \r
//\r
// Setup Peripherals (CS3-Interface1)\r
//\r
ldr r0, = 0x00025156\r
- str r0, [r1, #SmcSetCycles]\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
- // 0x00000002 = MemoryWidth: 32bit\r
- // 0x00000004 = Memory reads are synchronous\r
- // 0x00000040 = Memory writes are synchronous\r
- ldr r0, = 0x00000046\r
- str r0, [r1, #SmcSetOpMode] \r
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
- // 0x03800000 = ChipSelect3-Interface 1\r
- // 0x00400000 = CmdTypes: UpdateRegs\r
- ldr r0, = 0x03C00000\r
- str r0, [r1, #SmcDirectCmd] \r
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
-//\r
-// Setup VRAM (CS1-Interface0)\r
-//\r
+ bx lr\r
+\r
+\r
+// IN r1 SmcBase\r
+// IN r2 VideoSRamBase\r
+// NOTE: This code is been called before any stack has been setup. It means some registers\r
+// could be overwritten (case of 'r0')\r
+SMCInitializeVRAM\r
+ //\r
+ // Setup VRAM (CS1-Interface0)\r
+ //\r
ldr r0, = 0x00049249\r
- str r0, [r1, #SmcSetCycles]\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
- // 0x00000002 = MemoryWidth: 32bit\r
- // 0x00000004 = Memory reads are synchronous\r
- // 0x00000040 = Memory writes are synchronous\r
- ldr r0, = 0x00000046\r
- str r0, [r1, #SmcSetOpMode] \r
+ ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
- // 0x00800000 = ChipSelect1-Interface 0\r
- // 0x00400000 = CmdTypes: UpdateRegs\r
- ldr r0, = 0x00C00000\r
- str r0, [r1, #SmcDirectCmd] \r
+ ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
-//\r
-// Page mode setup for VRAM\r
-//\r
- //read current state \r
+ //\r
+ // Page mode setup for VRAM\r
+ //\r
+\r
+ // Read current state\r
ldr r0, [r2, #0] \r
ldr r0, [r2, #0] \r
ldr r0, = 0x00000000\r
str r0, [r2, #0] \r
ldr r0, [r2, #0] \r
\r
- //enable page mode \r
+ // Enable page mode\r
ldr r0, [r2, #0] \r
ldr r0, [r2, #0] \r
ldr r0, = 0x00000000\r
ldr r0, = 0x00900090\r
str r0, [r2, #0] \r
\r
- //confirm page mode enabled\r
+ // Confirm page mode enabled\r
ldr r0, [r2, #0] \r
ldr r0, [r2, #0] \r
ldr r0, = 0x00000000\r
projects / mirror_edk2.git / blobdiff