Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib...

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicNonSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
new file mode 100644 (file)
index 0000000..e5faa40
--- /dev/null
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
@@ -0,0 +1,97 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  \r
+*  This program and the accompanying materials                          \r
+*  are licensed and made available under the terms and conditions of the BSD License         \r
+*  which accompanies this distribution.  The full text of the license may be found at        \r
+*  http://opensource.org/licenses/bsd-license.php                                            \r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Drivers/PL390Gic.h>\r
+\r
+\r
+VOID\r
+EFIAPI\r
+PL390GicEnableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{      \r
+       /*\r
+        * Enable the CPU interface in Non-Secure world\r
+        * Note: The ICCICR register is banked when Security extensions are implemented  \r
+        */\r
+    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PL390GicEnableDistributor (\r
+  IN  INTN          GicDistributorBase\r
+  )\r
+{\r
+    /*\r
+     * Enable GIC distributor in Non-Secure world.\r
+     * Note: The ICDDCR register is banked when Security extensions are implemented\r
+     */\r
+    MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PL390GicSendSgiTo (\r
+  IN  INTN          GicDistributorBase,\r
+  IN  INTN          TargetListFilter,\r
+  IN  INTN          CPUTargetList\r
+  )\r
+{\r
+       MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
+}\r
+\r
+UINT32\r
+EFIAPI\r
+PL390GicAcknowledgeSgiFrom (\r
+  IN  INTN          GicInterruptInterfaceBase,\r
+  IN  INTN          CoreId\r
+  )\r
+{\r
+    INTN            InterruptId;\r
+\r
+    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+\r
+    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+       if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
+           //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+               MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+        return 1;\r
+    } else {\r
+        return 0;\r
+    }\r
+}\r
+\r
+UINT32\r
+EFIAPI\r
+PL390GicAcknowledgeSgi2From (\r
+  IN  INTN          GicInterruptInterfaceBase,\r
+  IN  INTN          CoreId,\r
+  IN  INTN          SgiId\r
+  )\r
+{\r
+    INTN            InterruptId;\r
+\r
+    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+\r
+    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+       if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
+           //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+               MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+        return 1;\r
+    } else {\r
+        return 0;\r
+    }\r
+}\r