- // Ensure all GIC interrupts are Non-Secure\r
- for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
+ // Ensure all GIC interrupts are Non-Secure\r
+ for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ }\r
+ } else {\r
+ // The secondary cores only set the Non Secure bit to their banked PPIs\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r