ArmPkg/ArmGicLib: Added function ArmGicSetSecureInterrupts() to define the secure...

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 244f9ecf2aaeadb89404ceba317cad7b8361642c..4f10e4e5129ded2c4aad6bf40be238404e15e476 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -12,7 +12,8 @@
 *\r
 **/\r
 \r
-#include <Uefi.h>\r
+#include <Base.h>\r
+#include <Library/DebugLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/ArmGicLib.h>\r
 \r
@@ -27,28 +28,57 @@ ArmGicSetupNonSecure (
   IN  INTN          GicInterruptInterfaceBase\r
   )\r
 {\r
-  UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
+  UINTN InterruptId;\r
+  UINTN CachedPriorityMask;\r
+  UINTN Index;\r
+\r
+  CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
 \r
   // Set priority Mask so that no interrupts get through to CPU\r
-  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
 \r
   // Check if there are any pending interrupts\r
   //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.\r
-  while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
+  while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
     // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-    UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
 \r
     // Write to End of interrupt signal\r
-    MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+    MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
   }\r
 \r
   // Ensure all GIC interrupts are Non-Secure\r
-  MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
-  MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
-  MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
+  for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+  }\r
 \r
   // Ensure all interrupts can get through the priority mask\r
-  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
+}\r
+\r
+/*\r
+ * This function configures the interrupts set by the mask to be secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicSetSecureInterrupts (\r
+  IN  UINTN         GicDistributorBase,\r
+  IN  UINTN*        GicSecureInterruptMask,\r
+  IN  UINTN         GicSecureInterruptMaskSize\r
+  )\r
+{\r
+  UINTN  Index;\r
+  UINT32 InterruptStatus;\r
+\r
+  // We must not have more interrupts defined by the mask than the number of available interrupts\r
+  ASSERT(GicSecureInterruptMaskSize <= (PcdGet32(PcdGicNumInterrupts) / 32));\r
+\r
+  // Set all the interrupts defined by the mask as Secure\r
+  for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
+    InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
+  }\r
 }\r
 \r
 VOID\r
@@ -57,14 +87,13 @@ ArmGicEnableInterruptInterface (
   IN  INTN          GicInterruptInterfaceBase\r
   )\r
 {\r
-  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);  /* Set Priority Mask to allow interrupts */\r
+  // Set Priority Mask to allow interrupts\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
 \r
-  /*\r
-   * Enable CPU interface in Secure world\r
-     * Enable CPU inteface in Non-secure World\r
-   * Signal Secure Interrupts to CPU using FIQ line *\r
-   */\r
-  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
+  // Enable CPU interface in Secure world\r
+  // Enable CPU inteface in Non-secure World\r
+  // Signal Secure Interrupts to CPU using FIQ line *\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
       ARM_GIC_ICCICR_ENABLE_SECURE |\r
       ARM_GIC_ICCICR_ENABLE_NS |\r
       ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
@@ -76,5 +105,6 @@ ArmGicEnableDistributor (
   IN  INTN          GicDistributorBase\r
   )\r
 {\r
-  MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1);               // turn on the GIC distributor\r
+  // Turn on the GIC distributor\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
 }\r