ArmPlatformPkg/ArmPlatformLib: Added support for ArmPlatformIsPrimaryCore()

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 57ae14150e7e4734d2bb455d2b71acd8b9f32f7c..bae76e441ba34c4a2f83d262bd57883efd3d5bbd 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
 *  \r
 *  This program and the accompanying materials                          \r
 *  are licensed and made available under the terms and conditions of the BSD License         \r
@@ -12,7 +12,10 @@
 *\r
 **/\r
 \r
-#include <Uefi.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/ArmGicLib.h>\r
 \r
@@ -23,37 +26,71 @@
 VOID\r
 EFIAPI\r
 ArmGicSetupNonSecure (\r
+  IN  UINTN         MpId,\r
   IN  INTN          GicDistributorBase,\r
   IN  INTN          GicInterruptInterfaceBase\r
   )\r
 {\r
   UINTN InterruptId;\r
   UINTN CachedPriorityMask;\r
+  UINTN Index;\r
 \r
   CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
 \r
   // Set priority Mask so that no interrupts get through to CPU\r
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
 \r
-  // Check if there are any pending interrupts\r
-  //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.\r
-  while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
-    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+  InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
 \r
-    // Write to End of interrupt signal\r
+  // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+  while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase))   {\r
+    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
     MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+\r
+    // Next\r
+    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
   }\r
 \r
-  // Ensure all GIC interrupts are Non-Secure\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
+  // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+  if (ArmPlatformIsPrimaryCore (MpId)) {\r
+    // Ensure all GIC interrupts are Non-Secure\r
+    for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
+      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+    }\r
+  } else {\r
+    // The secondary cores only set the Non Secure bit to their banked PPIs\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
+  }\r
 \r
   // Ensure all interrupts can get through the priority mask\r
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
 }\r
 \r
+/*\r
+ * This function configures the interrupts set by the mask to be secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicSetSecureInterrupts (\r
+  IN  UINTN         GicDistributorBase,\r
+  IN  UINTN*        GicSecureInterruptMask,\r
+  IN  UINTN         GicSecureInterruptMaskSize\r
+  )\r
+{\r
+  UINTN  Index;\r
+  UINT32 InterruptStatus;\r
+\r
+  // We must not have more interrupts defined by the mask than the number of available interrupts\r
+  ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r
+\r
+  // Set all the interrupts defined by the mask as Secure\r
+  for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
+    InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
+  }\r
+}\r
+\r
 VOID\r
 EFIAPI\r
 ArmGicEnableInterruptInterface (\r
@@ -64,7 +101,7 @@ ArmGicEnableInterruptInterface (
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
 \r
   // Enable CPU interface in Secure world\r
-  // Enable CPU inteface in Non-secure World\r
+  // Enable CPU interface in Non-secure World\r
   // Signal Secure Interrupts to CPU using FIQ line *\r
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
       ARM_GIC_ICCICR_ENABLE_SECURE |\r
@@ -72,6 +109,19 @@ ArmGicEnableInterruptInterface (
       ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
 }\r
 \r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  UINT32    ControlValue;\r
+\r
+  // Disable CPU interface in Secure world and Non-secure World\r
+  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
+}\r
+\r
 VOID\r
 EFIAPI\r
 ArmGicEnableDistributor (\r