/** @file\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
*\r
**/\r
\r
-#include <Uefi.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
-#include <Drivers/PL390Gic.h>\r
+#include <Library/ArmGicLib.h>\r
\r
/*\r
* This function configures the all interrupts to be Non-secure.\r
*/\r
VOID\r
EFIAPI\r
-PL390GicSetupNonSecure (\r
+ArmGicSetupNonSecure (\r
+ IN UINTN MpId,\r
IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);\r
+ UINTN InterruptId;\r
+ UINTN CachedPriorityMask;\r
+ UINTN Index;\r
+\r
+ CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
\r
// Set priority Mask so that no interrupts get through to CPU\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
+\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
\r
- // Check if there are any pending interrupts\r
- while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {\r
+ // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+ while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
- UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
\r
- // Write to End of interrupt signal\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+ // Next\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
}\r
\r
- // Ensure all GIC interrupts are Non-Secure\r
- MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
- MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
- MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
+ // Ensure all GIC interrupts are Non-Secure\r
+ for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ }\r
+ } else {\r
+ // The secondary cores only set the Non Secure bit to their banked PPIs\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
+ }\r
\r
// Ensure all interrupts can get through the priority mask\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
}\r
\r
+/*\r
+ * This function configures the interrupts set by the mask to be secure.\r
+ *\r
+ */\r
VOID\r
EFIAPI\r
-PL390GicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ArmGicSetSecureInterrupts (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN* GicSecureInterruptMask,\r
+ IN UINTN GicSecureInterruptMaskSize\r
)\r
{\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */\r
-\r
- /*\r
- * Enable CPU interface in Secure world\r
- * Enable CPU inteface in Non-secure World\r
- * Signal Secure Interrupts to CPU using FIQ line *\r
- */\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,\r
- GIC_ICCICR_ENABLE_SECURE(1) |\r
- GIC_ICCICR_ENABLE_NS(1) |\r
- GIC_ICCICR_ACK_CTL(0) |\r
- GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r
- GIC_ICCICR_USE_SBPR(0));\r
-}\r
+ UINTN Index;\r
+ UINT32 InterruptStatus;\r
\r
-VOID\r
-EFIAPI\r
-PL390GicEnableDistributor (\r
- IN INTN GicDistributorBase\r
- )\r
-{\r
- MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor\r
+ // We must not have more interrupts defined by the mask than the number of available interrupts\r
+ ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r
+\r
+ // Set all the interrupts defined by the mask as Secure\r
+ for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
+ InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
+ }\r
}\r
\r
VOID\r
EFIAPI\r
-PL390GicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList\r
+ArmGicEnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
+ // Set Priority Mask to allow interrupts\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
+\r
+ // Enable CPU interface in Secure world\r
+ // Enable CPU interface in Non-secure World\r
+ // Signal Secure Interrupts to CPU using FIQ line *\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
+ ARM_GIC_ICCICR_ENABLE_SECURE |\r
+ ARM_GIC_ICCICR_ENABLE_NS |\r
+ ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
}\r
\r
-UINT32\r
+VOID\r
EFIAPI\r
-PL390GicAcknowledgeSgiFrom (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId\r
+ArmGicDisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- INTN InterruptId;\r
-\r
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+ UINT32 ControlValue;\r
\r
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
- return 1;\r
- } else {\r
- return 0;\r
- }\r
+ // Disable CPU interface in Secure world and Non-secure World\r
+ ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
}\r
\r
-UINT32\r
+VOID\r
EFIAPI\r
-PL390GicAcknowledgeSgi2From (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId,\r
- IN INTN SgiId\r
+ArmGicEnableDistributor (\r
+ IN INTN GicDistributorBase\r
)\r
{\r
- INTN InterruptId;\r
-\r
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
-\r
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
- return 1;\r
- } else {\r
- return 0;\r
- }\r
+ // Turn on the GIC distributor\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
}\r
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