ArmPlatformPkg/ArmPlatformLib: Added support for ArmPlatformIsPrimaryCore()

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index e47e23d58103b84e16d663b617372feedef5cf5c..bae76e441ba34c4a2f83d262bd57883efd3d5bbd 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
 *  \r
 *  This program and the accompanying materials                          \r
 *  are licensed and made available under the terms and conditions of the BSD License         \r
@@ -14,6 +14,7 @@
 \r
 #include <Base.h>\r
 #include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
 #include <Library/DebugLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/ArmGicLib.h>\r
@@ -39,18 +40,19 @@ ArmGicSetupNonSecure (
   // Set priority Mask so that no interrupts get through to CPU\r
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
 \r
-  // Check if there are any pending interrupts\r
-  //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.\r
-  while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
-    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+  InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
 \r
-    // Write to End of interrupt signal\r
+  // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+  while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase))   {\r
+    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
     MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+\r
+    // Next\r
+    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
   }\r
 \r
   // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
-  if (IS_PRIMARY_CORE(MpId)) {\r
+  if (ArmPlatformIsPrimaryCore (MpId)) {\r
     // Ensure all GIC interrupts are Non-Secure\r
     for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
       MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r