-#define VTCR_EL23_PS_FIELD (16)\r
-#define TCR_EL23_T0SZ_MASK (0x1F << VTCR_EL23_T0SZ_FIELD)\r
-#define TCR_EL23_IRGN0_MASK (0x3 << VTCR_EL23_IRGN0_FIELD)\r
-#define TCR_EL23_ORGN0_MASK (0x3 << VTCR_EL23_ORGN0_FIELD)\r
-#define TCR_EL23_SH0_MASK (0x3 << VTCR_EL23_SH0_FIELD)\r
-#define TCR_EL23_TG0_MASK (0x1 << TCR_EL23_TG0_FIELD)\r
-#define TCR_EL23_PS_MASK (0x7 << VTCR_EL23_PS_FIELD)\r
-\r
-\r
-#define VTCR_EL2_T0SZ_FIELD (0)\r
-#define VTCR_EL2_SL0_FIELD (6)\r
-#define VTCR_EL2_IRGN0_FIELD (8)\r
-#define VTCR_EL2_ORGN0_FIELD (10)\r
-#define VTCR_EL2_SH0_FIELD (12)\r
-#define VTCR_EL2_TG0_FIELD (14)\r
-#define VTCR_EL2_PS_FIELD (16)\r
-#define VTCR_EL2_T0SZ_MASK (0x1F << VTCR_EL2_T0SZ_FIELD)\r
-#define VTCR_EL2_SL0_MASK (0x1F << VTCR_EL2_SL0_FIELD)\r
-#define VTCR_EL2_IRGN0_MASK (0x3 << VTCR_EL2_IRGN0_FIELD)\r
-#define VTCR_EL2_ORGN0_MASK (0x3 << VTCR_EL2_ORGN0_FIELD)\r
-#define VTCR_EL2_SH0_MASK (0x3 << VTCR_EL2_SH0_FIELD)\r
-#define VTCR_EL2_TG0_MASK (0x1 << VTCR_EL2_TG0_FIELD)\r
-#define VTCR_EL2_PS_MASK (0x7 << VTCR_EL2_PS_FIELD)\r
-\r
-\r
-#define TCR_RGN_OUTER_NON_CACHEABLE (0x0 << 10)\r
-#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1 << 10)\r
-#define TCR_RGN_OUTER_WRITE_THROUGH (0x2 << 10)\r
-#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3 << 10)\r
-\r
-#define TCR_RGN_INNER_NON_CACHEABLE (0x0 << 8)\r
-#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1 << 8)\r
-#define TCR_RGN_INNER_WRITE_THROUGH (0x2 << 8)\r
-#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3 << 8)\r
-\r
-#define TCR_SH_NON_SHAREABLE (0x0 << 12)\r
-#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)\r
-#define TCR_SH_INNER_SHAREABLE (0x3 << 12)\r
-\r
-#define TCR_PASZ_32BITS_4GB (0x0)\r
-#define TCR_PASZ_36BITS_64GB (0x1)\r
-#define TCR_PASZ_40BITS_1TB (0x2)\r
-#define TCR_PASZ_42BITS_4TB (0x3)\r
-#define TCR_PASZ_44BITS_16TB (0x4)\r
-#define TCR_PASZ_48BITS_256TB (0x5)\r
+#define TCR_EL23_PS_FIELD (16)\r
+#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)\r
+#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)\r
+#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)\r
+#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)\r
+#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)\r
+#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)\r
+\r
+\r
+#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)\r
+\r
+#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)\r
+#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)\r
+#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)\r
+#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)\r
+\r
+#define TCR_SH_NON_SHAREABLE (0x0UL << 12)\r
+#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)\r
+#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)\r
+\r
+#define TCR_PASZ_32BITS_4GB (0x0UL)\r
+#define TCR_PASZ_36BITS_64GB (0x1UL)\r
+#define TCR_PASZ_40BITS_1TB (0x2UL)\r
+#define TCR_PASZ_42BITS_4TB (0x3UL)\r
+#define TCR_PASZ_44BITS_16TB (0x4UL)\r
+#define TCR_PASZ_48BITS_256TB (0x5UL)\r