/** @file\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
-#ifndef __ARM_V7_H__\r
-#define __ARM_V7_H__\r
-\r
-// Domain Access Control Register\r
-#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
-\r
-#define TTBR_NOT_OUTER_SHAREABLE BIT5\r
-#define TTBR_RGN_OUTER_NON_CACHEABLE 0\r
-#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3\r
-#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4\r
-#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)\r
-#define TTBR_SHAREABLE BIT1\r
-#define TTBR_NON_SHAREABLE 0\r
-#define TTBR_INNER_CACHEABLE BIT0\r
-#define TTBR_NON_INNER_CACHEABLE BIT0\r
-#define TTBR_RGN_INNER_NON_CACHEABLE 0\r
-#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6\r
-#define TTBR_RGN_INNER_WRITE_THROUGH BIT0\r
-#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)\r
-\r
-#define TTBR_WRITE_THROUGH_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )\r
-#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC )\r
-#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )\r
-#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )\r
-\r
-\r
-#define TRANSLATION_TABLE_SECTION_COUNT 4096\r
-#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)\r
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)\r
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)\r
-\r
-#define TRANSLATION_TABLE_PAGE_COUNT 256\r
-#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)\r
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)\r
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)\r
-\r
-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
-\r
-// Translation table descriptor types\r
-#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))\r
-#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)\r
-#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)\r
-#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))\r
-#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
-#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)\r
-\r
-// Translation table descriptor types\r
-#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)\r
-\r
-// Section descriptor definitions\r
-#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)\r
-#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)\r
-#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)\r
-\r
-#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)\r
-#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)\r
-#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)\r
-\r
-#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)\r
-\r
-#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)\r
-#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)\r
-#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)\r
-\r
-#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))\r
-\r
-#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))\r
-\r
-#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)\r
-#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)\r
-#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)\r
-\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)\r
-\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \\r
- ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \\r
- ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_PAGE_XN_MASK))\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \\r
- (((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \\r
- (((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))\r
-\r
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)\r
-\r
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \\r
- (((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \\r
- (((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))\r
+#ifndef ARM_V7_H_\r
+#define ARM_V7_H_\r
\r
+#include <Chipset/ArmV7Mmu.h>\r
\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)\r
+// ARM Interrupt ID in Exception Table\r
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r
\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)\r
-#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
-#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20\r
+// ID_PFR1 - ARM Processor Feature Register 1 definitions\r
+#define ARM_PFR1_SEC (0xFUL << 4)\r
+#define ARM_PFR1_TIMER (0xFUL << 16)\r
+#define ARM_PFR1_GIC (0xFUL << 28)\r
\r
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)\r
-#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)\r
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)\r
-#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12\r
-\r
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_DEVICE(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
-#define TT_DESCRIPTOR_SECTION_UNCACHED(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
-\r
-#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)\r
-#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
-#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)\r
-#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)\r
-\r
-// Cortex A9 feature bit definitions\r
-#define A9_FEATURE_PARITY (1<<9)\r
-#define A9_FEATURE_AOW (1<<8)\r
-#define A9_FEATURE_EXCL (1<<7)\r
-#define A9_FEATURE_SMP (1<<6)\r
-#define A9_FEATURE_FOZ (1<<3)\r
-#define A9_FEATURE_DPREF (1<<2)\r
-#define A9_FEATURE_HINT (1<<1)\r
-#define A9_FEATURE_FWD (1<<0)\r
-\r
-// SCU register offsets & masks\r
-#define SCU_CONTROL_OFFSET 0x0\r
-#define SCU_CONFIG_OFFSET 0x4\r
-#define SCU_INVALL_OFFSET 0xC\r
-#define SCU_FILT_START_OFFSET 0x40\r
-#define SCU_FILT_END_OFFSET 0x44\r
-#define SCU_SACR_OFFSET 0x50\r
-#define SCU_SSACR_OFFSET 0x54\r
-\r
-#define SMP_GIC_CPUIF_BASE 0x100\r
-#define SMP_GIC_DIST_BASE 0x1000\r
-\r
-// CPACR - Coprocessor Access Control Register defintions\r
-#define CPACR_CP_DENIED(cp) 0x00\r
-#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
-#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r
-#define CPACR_ASEDIS (1 << 31)\r
-#define CPACR_D32DIS (1 << 30)\r
-#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r
-\r
-// NSACR - Non-Secure Access Control Register defintions\r
-#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r
-#define NSACR_NSD32DIS (1 << 14)\r
-#define NSACR_NSASEDIS (1 << 15)\r
-#define NSACR_PLE (1 << 16)\r
-#define NSACR_TL (1 << 17)\r
-#define NSACR_NS_SMP (1 << 18)\r
-#define NSACR_RFR (1 << 19)\r
-\r
-// SCR - Secure Configuration Register defintions\r
-#define SCR_NS (1 << 0)\r
-#define SCR_IRQ (1 << 1)\r
-#define SCR_FIQ (1 << 2)\r
-#define SCR_EA (1 << 3)\r
-#define SCR_FW (1 << 4)\r
-#define SCR_AW (1 << 5)\r
+// Domain Access Control Register\r
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
+\r
+// CPSR - Coprocessor Status Register definitions\r
+#define CPSR_MODE_USER 0x10\r
+#define CPSR_MODE_FIQ 0x11\r
+#define CPSR_MODE_IRQ 0x12\r
+#define CPSR_MODE_SVC 0x13\r
+#define CPSR_MODE_ABORT 0x17\r
+#define CPSR_MODE_HYP 0x1A\r
+#define CPSR_MODE_UNDEFINED 0x1B\r
+#define CPSR_MODE_SYSTEM 0x1F\r
+#define CPSR_MODE_MASK 0x1F\r
+#define CPSR_ASYNC_ABORT (1 << 8)\r
+#define CPSR_IRQ (1 << 7)\r
+#define CPSR_FIQ (1 << 6)\r
+\r
+// CPACR - Coprocessor Access Control Register definitions\r
+#define CPACR_CP_DENIED(cp) 0x00\r
+#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
+#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r
+#define CPACR_ASEDIS (1 << 31)\r
+#define CPACR_D32DIS (1 << 30)\r
+#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r
+\r
+// NSACR - Non-Secure Access Control Register definitions\r
+#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r
+#define NSACR_NSD32DIS (1 << 14)\r
+#define NSACR_NSASEDIS (1 << 15)\r
+#define NSACR_PLE (1 << 16)\r
+#define NSACR_TL (1 << 17)\r
+#define NSACR_NS_SMP (1 << 18)\r
+#define NSACR_RFR (1 << 19)\r
+\r
+// SCR - Secure Configuration Register definitions\r
+#define SCR_NS (1 << 0)\r
+#define SCR_IRQ (1 << 1)\r
+#define SCR_FIQ (1 << 2)\r
+#define SCR_EA (1 << 3)\r
+#define SCR_FW (1 << 4)\r
+#define SCR_AW (1 << 5)\r
+\r
+// MIDR - Main ID Register definitions\r
+#define ARM_CPU_TYPE_SHIFT 4\r
+#define ARM_CPU_TYPE_MASK 0xFFF\r
+#define ARM_CPU_TYPE_AEMV8 0xD0F\r
+#define ARM_CPU_TYPE_A53 0xD03\r
+#define ARM_CPU_TYPE_A57 0xD07\r
+#define ARM_CPU_TYPE_A15 0xC0F\r
+#define ARM_CPU_TYPE_A12 0xC0D\r
+#define ARM_CPU_TYPE_A9 0xC09\r
+#define ARM_CPU_TYPE_A7 0xC07\r
+#define ARM_CPU_TYPE_A5 0xC05\r
+\r
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
+\r
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r
\r
VOID\r
EFIAPI\r
VOID\r
);\r
\r
-VOID\r
-EFIAPI\r
-ArmWriteNsacr (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteScr (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteVMBar (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteVBar (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-ArmReadVBar (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCPACR (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmEnableVFP (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCallWFI (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidScu (\r
- VOID\r
- );\r
-\r
-\r
UINTN\r
EFIAPI\r
-ArmGetScuBaseAddress (\r
+ArmReadCbar (\r
VOID\r
);\r
\r
-UINT32\r
+UINTN\r
EFIAPI\r
-ArmIsScuEnable(\r
+ArmReadTpidrurw (\r
VOID\r
);\r
\r
VOID\r
EFIAPI\r
-ArmWriteAuxCr (\r
- IN UINT32 Bit\r
+ArmWriteTpidrurw (\r
+ UINTN Value\r
);\r
\r
UINT32\r
EFIAPI\r
-ArmReadAuxCr (\r
+ArmReadNsacr (\r
VOID\r
);\r
\r
VOID\r
EFIAPI\r
-ArmSetAuxCrBit (\r
- IN UINT32 Bits\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmSetupSmpNonSecure (\r
- IN UINTN CoreId\r
+ArmWriteNsacr (\r
+ IN UINT32 Nsacr\r
);\r
\r
-\r
-UINTN \r
-EFIAPI\r
-ArmReadCbar(\r
-VOID\r
-);\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidateInstructionAndDataTlb(\r
-VOID\r
-);\r
-\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadMpidr(\r
-VOID\r
-);\r
-\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadTpidrurw(\r
-VOID\r
-);\r
-\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteTpidrurw(\r
-UINTN Value\r
-);\r
-\r
-#endif // __ARM_V7_H__\r
+#endif // ARM_V7_H_\r
projects / mirror_edk2.git / blobdiff