ArmPkg/PL35xSmc: Split the SMC initialization in multiple Chip Select initialization...

[mirror_edk2.git] / ArmPkg / Include / Drivers / PL354Smc.h

diff --git a/ArmPkg/Include/Drivers/PL354Smc.h b/ArmPkg/Include/Drivers/PL354Smc.h
new file mode 100644 (file)
index 0000000..0da47f9
--- /dev/null
+++ b/ArmPkg/Include/Drivers/PL354Smc.h
@@ -0,0 +1,57 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef PL354SMC_H_\r
+#define PL354SMC_H_\r
+\r
+#define PL354_SMC_DIRECT_CMD_OFFSET  0x10\r
+#define PL354_SMC_SET_CYCLES_OFFSET  0x14\r
+#define PL354_SMC_SET_OPMODE_OFFSET  0x18\r
+\r
+#define PL354_SMC_DIRECT_CMD_ADDR(addr)             ((addr) & 0xFFFFF)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE           (1 << 20)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE   (3 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE        (2 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE          (1 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI    (0 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip)   (((interf) << 25) | ((chip) << 23))\r
+\r
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8                (0 << 0)\r
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16               (1 << 0)\r
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32               (2 << 0)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_SYNC                (1 << 2)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1      (0 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4      (1 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8      (2 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16     (3 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32     (4 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT   (5 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_SYNC                (1 << 6)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1      (0 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4      (1 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8      (2 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16     (3 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32     (4 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT   (5 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_BAA                    (1 << 10)\r
+#define PL354_SMC_SET_OPMODE_SET_ADV                    (1 << 11)\r
+#define PL354_SMC_SET_OPMODE_SET_BLS                    (1 << 12)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY        (0 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32         (1 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64         (2 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128        (3 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256        (4 << 13)\r
+\r
+\r
+#endif\r