\r
// The ARM Architecture Reference Manual for ARMv8-A defines up\r
// to 7 levels of cache, L1 through L7.\r
\r
// The ARM Architecture Reference Manual for ARMv8-A defines up\r
// to 7 levels of cache, L1 through L7.\r
- UINT32 InD :1; ///< Instruction not Data bit\r
- UINT32 Level :3; ///< Cache level (zero based)\r
- UINT32 TnD :1; ///< Allocation not Data bit\r
- UINT32 Reserved :27; ///< Reserved, RES0\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
+ UINT32 InD : 1; ///< Instruction not Data bit\r
+ UINT32 Level : 3; ///< Cache level (zero based)\r
+ UINT32 TnD : 1; ///< Allocation not Data bit\r
+ UINT32 Reserved : 27; ///< Reserved, RES0\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
/// Select the data or unified cache\r
CsselrCacheTypeDataOrUnified = 0,\r
/// Select the instruction cache\r
/// Select the data or unified cache\r
CsselrCacheTypeDataOrUnified = 0,\r
/// Select the instruction cache\r
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
- UINT64 Associativity :10; ///< Associativity - 1\r
- UINT64 NumSets :15; ///< Number of sets in the cache -1\r
- UINT64 Unknown :4; ///< Reserved, UNKNOWN\r
- UINT64 Reserved :32; ///< Reserved, RES0\r
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)\r
+ UINT64 Associativity : 10; ///< Associativity - 1\r
+ UINT64 NumSets : 15; ///< Number of sets in the cache -1\r
+ UINT64 Unknown : 4; ///< Reserved, UNKNOWN\r
+ UINT64 Reserved : 32; ///< Reserved, RES0\r
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
- UINT64 Associativity :21; ///< Associativity - 1\r
- UINT64 Reserved1 :8; ///< Reserved, RES0\r
- UINT64 NumSets :24; ///< Number of sets in the cache -1\r
- UINT64 Reserved2 :8; ///< Reserved, RES0\r
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)\r
+ UINT64 Associativity : 21; ///< Associativity - 1\r
+ UINT64 Reserved1 : 8; ///< Reserved, RES0\r
+ UINT64 NumSets : 24; ///< Number of sets in the cache -1\r
+ UINT64 Reserved2 : 8; ///< Reserved, RES0\r
- UINT32 NumSets :24; ///< Number of sets in the cache - 1\r
- UINT32 Reserved :8; ///< Reserved, RES0\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
+ UINT32 NumSets : 24; ///< Number of sets in the cache - 1\r
+ UINT32 Reserved : 8; ///< Reserved, RES0\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
- UINT32 Ctype1 : 3; ///< Level 1 cache type\r
- UINT32 Ctype2 : 3; ///< Level 2 cache type\r
- UINT32 Ctype3 : 3; ///< Level 3 cache type\r
- UINT32 Ctype4 : 3; ///< Level 4 cache type\r
- UINT32 Ctype5 : 3; ///< Level 5 cache type\r
- UINT32 Ctype6 : 3; ///< Level 6 cache type\r
- UINT32 Ctype7 : 3; ///< Level 7 cache type\r
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r
- UINT32 LoC : 3; ///< Level of Coherency\r
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r
- UINT32 Icb : 3; ///< Inner Cache Boundary\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
+ UINT32 Ctype1 : 3; ///< Level 1 cache type\r
+ UINT32 Ctype2 : 3; ///< Level 2 cache type\r
+ UINT32 Ctype3 : 3; ///< Level 3 cache type\r
+ UINT32 Ctype4 : 3; ///< Level 4 cache type\r
+ UINT32 Ctype5 : 3; ///< Level 5 cache type\r
+ UINT32 Ctype6 : 3; ///< Level 6 cache type\r
+ UINT32 Ctype7 : 3; ///< Level 7 cache type\r
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r
+ UINT32 LoC : 3; ///< Level of Coherency\r
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r
+ UINT32 Icb : 3; ///< Inner Cache Boundary\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r