* SMC function IDs for Standard Service queries\r
*/\r
\r
-#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00\r
-#define ARM_SMC_ID_STD_UID 0x8400ff01\r
+#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00\r
+#define ARM_SMC_ID_STD_UID 0x8400ff01\r
/* 0x8400ff02 is reserved */\r
-#define ARM_SMC_ID_STD_REVISION 0x8400ff03\r
+#define ARM_SMC_ID_STD_REVISION 0x8400ff03\r
\r
/*\r
* The 'Standard Service Call UID' is supposed to return the Standard\r
* Service UUID. This is a 128-bit value.\r
*/\r
-#define ARM_SMC_STD_UUID0 0x108d905b\r
-#define ARM_SMC_STD_UUID1 0x47e8f863\r
-#define ARM_SMC_STD_UUID2 0xfbc02dae\r
-#define ARM_SMC_STD_UUID3 0xe2f64156\r
+#define ARM_SMC_STD_UUID0 0x108d905b\r
+#define ARM_SMC_STD_UUID1 0x47e8f863\r
+#define ARM_SMC_STD_UUID2 0xfbc02dae\r
+#define ARM_SMC_STD_UUID3 0xe2f64156\r
\r
/*\r
* ARM Standard Service Calls revision numbers\r
* The current revision is: 0.1\r
*/\r
-#define ARM_SMC_STD_REVISION_MAJOR 0x0\r
-#define ARM_SMC_STD_REVISION_MINOR 0x1\r
+#define ARM_SMC_STD_REVISION_MAJOR 0x0\r
+#define ARM_SMC_STD_REVISION_MINOR 0x1\r
\r
/*\r
* Management Mode (MM) calls cover a subset of the Standard Service Call range.\r
* The list below is not exhaustive.\r
*/\r
-#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040\r
-#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040\r
+#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040\r
+#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040\r
\r
// Request service from secure standalone MM environment\r
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041\r
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041\r
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041\r
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041\r
\r
/* Generic ID when using AArch32 or AArch64 execution state */\r
#ifdef MDE_CPU_AARCH64\r
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64\r
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64\r
#endif\r
#ifdef MDE_CPU_ARM\r
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32\r
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32\r
#endif\r
\r
/* MM return error codes */\r
-#define ARM_SMC_MM_RET_SUCCESS 0\r
-#define ARM_SMC_MM_RET_NOT_SUPPORTED -1\r
-#define ARM_SMC_MM_RET_INVALID_PARAMS -2\r
-#define ARM_SMC_MM_RET_DENIED -3\r
-#define ARM_SMC_MM_RET_NO_MEMORY -4\r
+#define ARM_SMC_MM_RET_SUCCESS 0\r
+#define ARM_SMC_MM_RET_NOT_SUPPORTED -1\r
+#define ARM_SMC_MM_RET_INVALID_PARAMS -2\r
+#define ARM_SMC_MM_RET_DENIED -3\r
+#define ARM_SMC_MM_RET_NO_MEMORY -4\r
\r
// ARM Architecture Calls\r
-#define SMCCC_VERSION 0x80000000\r
-#define SMCCC_ARCH_FEATURES 0x80000001\r
-#define SMCCC_ARCH_SOC_ID 0x80000002\r
-#define SMCCC_ARCH_WORKAROUND_1 0x80008000\r
-#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF\r
+#define SMCCC_VERSION 0x80000000\r
+#define SMCCC_ARCH_FEATURES 0x80000001\r
+#define SMCCC_ARCH_SOC_ID 0x80000002\r
+#define SMCCC_ARCH_WORKAROUND_1 0x80008000\r
+#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF\r
\r
#define SMC_ARCH_CALL_SUCCESS 0\r
-#define SMC_ARCH_CALL_NOT_SUPPORTED -1\r
-#define SMC_ARCH_CALL_NOT_REQUIRED -2\r
-#define SMC_ARCH_CALL_INVALID_PARAMETER -3\r
+#define SMC_ARCH_CALL_NOT_SUPPORTED -1\r
+#define SMC_ARCH_CALL_NOT_REQUIRED -2\r
+#define SMC_ARCH_CALL_INVALID_PARAMETER -3\r
\r
/*\r
* Power State Coordination Interface (PSCI) calls cover a subset of the\r
((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)\r
\r
/* PSCI return error codes */\r
-#define ARM_SMC_PSCI_RET_SUCCESS 0\r
-#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1\r
-#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2\r
-#define ARM_SMC_PSCI_RET_DENIED -3\r
-#define ARM_SMC_PSCI_RET_ALREADY_ON -4\r
-#define ARM_SMC_PSCI_RET_ON_PENDING -5\r
-#define ARM_SMC_PSCI_RET_INTERN_FAIL -6\r
-#define ARM_SMC_PSCI_RET_NOT_PRESENT -7\r
-#define ARM_SMC_PSCI_RET_DISABLED -8\r
+#define ARM_SMC_PSCI_RET_SUCCESS 0\r
+#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1\r
+#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2\r
+#define ARM_SMC_PSCI_RET_DENIED -3\r
+#define ARM_SMC_PSCI_RET_ALREADY_ON -4\r
+#define ARM_SMC_PSCI_RET_ON_PENDING -5\r
+#define ARM_SMC_PSCI_RET_INTERN_FAIL -6\r
+#define ARM_SMC_PSCI_RET_NOT_PRESENT -7\r
+#define ARM_SMC_PSCI_RET_DISABLED -8\r
\r
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \\r
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))\r
#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)\r
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)\r
\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3\r
\r
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0\r
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1\r
/*\r
* SMC function IDs for Trusted OS Service queries\r
*/\r
-#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00\r
-#define ARM_SMC_ID_TOS_UID 0xbf00ff01\r
+#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00\r
+#define ARM_SMC_ID_TOS_UID 0xbf00ff01\r
/* 0xbf00ff02 is reserved */\r
-#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03\r
+#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03\r
\r
#endif // ARM_STD_SMC_H_\r