ArmPkg: Apply uncrustify changes

[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 79ea755777a9a6f2cb042794f552ed38d63f631a..e4d0476090c7b72dff82aeae4280e0bccf5f11d9 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -15,13 +15,13 @@
 \r
 #ifdef MDE_CPU_ARM\r
   #include <Chipset/ArmV7.h>\r
-#elif defined(MDE_CPU_AARCH64)\r
+#elif defined (MDE_CPU_AARCH64)\r
   #include <Chipset/AArch64.h>\r
 #else\r
- #error "Unknown chipset."\r
+  #error "Unknown chipset."\r
 #endif\r
 \r
-#define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
+#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC | EFI_MEMORY_WC |  \\r
                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
                                      EFI_MEMORY_UCE)\r
 \r
@@ -50,17 +50,21 @@ typedef enum {
   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
 } ARM_MEMORY_REGION_ATTRIBUTES;\r
 \r
-#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr)  ((UINT32)(attr) & 1)\r
 \r
 typedef struct {\r
-  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
-  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
-  UINT64                        Length;\r
-  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
+  EFI_PHYSICAL_ADDRESS            PhysicalBase;\r
+  EFI_VIRTUAL_ADDRESS             VirtualBase;\r
+  UINT64                          Length;\r
+  ARM_MEMORY_REGION_ATTRIBUTES    Attributes;\r
 } ARM_MEMORY_REGION_DESCRIPTOR;\r
 \r
-typedef VOID (*CACHE_OPERATION)(VOID);\r
-typedef VOID (*LINE_OPERATION)(UINTN);\r
+typedef VOID (*CACHE_OPERATION)(\r
+  VOID\r
+  );\r
+typedef VOID (*LINE_OPERATION)(\r
+  UINTN\r
+  );\r
 \r
 //\r
 // ARM Processor Mode\r
@@ -80,34 +84,34 @@ typedef enum {
 //\r
 // ARM Cpu IDs\r
 //\r
-#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
-#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
-#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
-#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
-#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
-#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
-\r
-#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
+#define ARM_CPU_IMPLEMENTER_MASK      (0xFFU << 24)\r
+#define ARM_CPU_IMPLEMENTER_ARMLTD    (0x41U << 24)\r
+#define ARM_CPU_IMPLEMENTER_DEC       (0x44U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MOT       (0x4DU << 24)\r
+#define ARM_CPU_IMPLEMENTER_QUALCOMM  (0x51U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MARVELL   (0x56U << 24)\r
+\r
+#define ARM_CPU_PRIMARY_PART_MASK       (0xFFF << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA5   (0xC05 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA7   (0xC07 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA8   (0xC08 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA9   (0xC09 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA15  (0xC0F << 4)\r
 \r
 //\r
 // ARM MP Core IDs\r
 //\r
-#define ARM_CORE_AFF0         0xFF\r
-#define ARM_CORE_AFF1         (0xFF << 8)\r
-#define ARM_CORE_AFF2         (0xFF << 16)\r
-#define ARM_CORE_AFF3         (0xFFULL << 32)\r
-\r
-#define ARM_CORE_MASK         ARM_CORE_AFF0\r
-#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
-#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
-#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
-#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
-#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
+#define ARM_CORE_AFF0  0xFF\r
+#define ARM_CORE_AFF1  (0xFF << 8)\r
+#define ARM_CORE_AFF2  (0xFF << 16)\r
+#define ARM_CORE_AFF3  (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK     ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK  ARM_CORE_AFF1\r
+#define GET_CORE_ID(MpId)            ((MpId) & ARM_CORE_MASK)\r
+#define GET_CLUSTER_ID(MpId)         (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
+#define GET_MPID(ClusterId, CoreId)  (((ClusterId) << 8) | (CoreId))\r
+#define PRIMARY_CORE_ID  (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r
 /** Reads the CCSIDR register for the specified cache.\r
 \r
@@ -118,7 +122,7 @@ typedef enum {
 **/\r
 UINTN\r
 ReadCCSIDR (\r
-  IN UINT32 CSSELR\r
+  IN UINT32  CSSELR\r
   );\r
 \r
 /** Reads the CCSIDR2 for the specified cache.\r
@@ -129,7 +133,7 @@ ReadCCSIDR (
 **/\r
 UINT32\r
 ReadCCSIDR2 (\r
-  IN UINT32 CSSELR\r
+  IN UINT32  CSSELR\r
   );\r
 \r
 /** Reads the Cache Level ID (CLIDR) register.\r
@@ -183,7 +187,6 @@ ArmInvalidateDataCache (
   VOID\r
   );\r
 \r
-\r
 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCache (\r
@@ -205,31 +208,31 @@ ArmInvalidateInstructionCache (
 VOID\r
 EFIAPI\r
 ArmInvalidateDataCacheEntryByMVA (\r
-  IN  UINTN   Address\r
+  IN  UINTN  Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r
 ArmCleanDataCacheEntryToPoUByMVA (\r
-  IN  UINTN   Address\r
+  IN  UINTN  Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r
 ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
-  IN  UINTN   Address\r
+  IN  UINTN  Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r
 ArmCleanDataCacheEntryByMVA (\r
-IN  UINTN   Address\r
-);\r
+  IN  UINTN  Address\r
+  );\r
 \r
 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r
-  IN  UINTN   Address\r
+  IN  UINTN  Address\r
   );\r
 \r
 VOID\r
@@ -352,8 +355,8 @@ ArmInvalidateTlb (
 VOID\r
 EFIAPI\r
 ArmUpdateTranslationTableEntry (\r
-  IN  VOID     *TranslationTableEntry,\r
-  IN  VOID     *Mva\r
+  IN  VOID  *TranslationTableEntry,\r
+  IN  VOID  *Mva\r
   );\r
 \r
 VOID\r
@@ -371,7 +374,7 @@ ArmSetTTBR0 (
 VOID\r
 EFIAPI\r
 ArmSetTTBCR (\r
-  IN  UINT32 Bits\r
+  IN  UINT32  Bits\r
   );\r
 \r
 VOID *\r
@@ -431,7 +434,7 @@ ArmInstructionSynchronizationBarrier (
 VOID\r
 EFIAPI\r
 ArmWriteVBar (\r
-  IN  UINTN   VectorBase\r
+  IN  UINTN  VectorBase\r
   );\r
 \r
 UINTN\r
@@ -443,7 +446,7 @@ ArmReadVBar (
 VOID\r
 EFIAPI\r
 ArmWriteAuxCr (\r
-  IN  UINT32    Bit\r
+  IN  UINT32  Bit\r
   );\r
 \r
 UINT32\r
@@ -455,13 +458,13 @@ ArmReadAuxCr (
 VOID\r
 EFIAPI\r
 ArmSetAuxCrBit (\r
-  IN  UINT32    Bits\r
+  IN  UINT32  Bits\r
   );\r
 \r
 VOID\r
 EFIAPI\r
 ArmUnsetAuxCrBit (\r
-  IN  UINT32    Bits\r
+  IN  UINT32  Bits\r
   );\r
 \r
 VOID\r
@@ -504,7 +507,7 @@ ArmReadCpacr (
 VOID\r
 EFIAPI\r
 ArmWriteCpacr (\r
-  IN  UINT32   Access\r
+  IN  UINT32  Access\r
   );\r
 \r
 VOID\r
@@ -534,7 +537,7 @@ ArmReadScr (
 VOID\r
 EFIAPI\r
 ArmWriteScr (\r
-  IN  UINT32   Value\r
+  IN  UINT32  Value\r
   );\r
 \r
 UINT32\r
@@ -546,7 +549,7 @@ ArmReadMVBar (
 VOID\r
 EFIAPI\r
 ArmWriteMVBar (\r
-  IN  UINT32   VectorMonitorBase\r
+  IN  UINT32  VectorMonitorBase\r
   );\r
 \r
 UINT32\r
@@ -558,7 +561,7 @@ ArmReadSctlr (
 VOID\r
 EFIAPI\r
 ArmWriteSctlr (\r
-  IN  UINT32   Value\r
+  IN  UINT32  Value\r
   );\r
 \r
 UINTN\r
@@ -570,10 +573,9 @@ ArmReadHVBar (
 VOID\r
 EFIAPI\r
 ArmWriteHVBar (\r
-  IN  UINTN   HypModeVectorBase\r
+  IN  UINTN  HypModeVectorBase\r
   );\r
 \r
-\r
 //\r
 // Helper functions for accessing CPU ACTLR\r
 //\r
@@ -587,28 +589,28 @@ ArmReadCpuActlr (
 VOID\r
 EFIAPI\r
 ArmWriteCpuActlr (\r
-  IN  UINTN Val\r
+  IN  UINTN  Val\r
   );\r
 \r
 VOID\r
 EFIAPI\r
 ArmSetCpuActlrBit (\r
-  IN  UINTN    Bits\r
+  IN  UINTN  Bits\r
   );\r
 \r
 VOID\r
 EFIAPI\r
 ArmUnsetCpuActlrBit (\r
-  IN  UINTN    Bits\r
+  IN  UINTN  Bits\r
   );\r
 \r
 //\r
 // Accessors for the architected generic timer registers\r
 //\r
 \r
-#define ARM_ARCH_TIMER_ENABLE           (1 << 0)\r
-#define ARM_ARCH_TIMER_IMASK            (1 << 1)\r
-#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)\r
+#define ARM_ARCH_TIMER_ENABLE   (1 << 0)\r
+#define ARM_ARCH_TIMER_IMASK    (1 << 1)\r
+#define ARM_ARCH_TIMER_ISTATUS  (1 << 2)\r
 \r
 UINTN\r
 EFIAPI\r
@@ -619,7 +621,7 @@ ArmReadCntFrq (
 VOID\r
 EFIAPI\r
 ArmWriteCntFrq (\r
-  UINTN   FreqInHz\r
+  UINTN  FreqInHz\r
   );\r
 \r
 UINT64\r
@@ -637,7 +639,7 @@ ArmReadCntkCtl (
 VOID\r
 EFIAPI\r
 ArmWriteCntkCtl (\r
-  UINTN   Val\r
+  UINTN  Val\r
   );\r
 \r
 UINTN\r
@@ -649,7 +651,7 @@ ArmReadCntpTval (
 VOID\r
 EFIAPI\r
 ArmWriteCntpTval (\r
-  UINTN   Val\r
+  UINTN  Val\r
   );\r
 \r
 UINTN\r
@@ -661,7 +663,7 @@ ArmReadCntpCtl (
 VOID\r
 EFIAPI\r
 ArmWriteCntpCtl (\r
-  UINTN   Val\r
+  UINTN  Val\r
   );\r
 \r
 UINTN\r
@@ -673,7 +675,7 @@ ArmReadCntvTval (
 VOID\r
 EFIAPI\r
 ArmWriteCntvTval (\r
-  UINTN   Val\r
+  UINTN  Val\r
   );\r
 \r
 UINTN\r
@@ -685,7 +687,7 @@ ArmReadCntvCtl (
 VOID\r
 EFIAPI\r
 ArmWriteCntvCtl (\r
-  UINTN   Val\r
+  UINTN  Val\r
   );\r
 \r
 UINT64\r
@@ -703,7 +705,7 @@ ArmReadCntpCval (
 VOID\r
 EFIAPI\r
 ArmWriteCntpCval (\r
-  UINT64   Val\r
+  UINT64  Val\r
   );\r
 \r
 UINT64\r
@@ -715,7 +717,7 @@ ArmReadCntvCval (
 VOID\r
 EFIAPI\r
 ArmWriteCntvCval (\r
-  UINT64   Val\r
+  UINT64  Val\r
   );\r
 \r
 UINT64\r
@@ -727,7 +729,7 @@ ArmReadCntvOff (
 VOID\r
 EFIAPI\r
 ArmWriteCntvOff (\r
-  UINT64   Val\r
+  UINT64  Val\r
   );\r
 \r
 UINTN\r
@@ -736,7 +738,6 @@ ArmGetPhysicalAddressBits (
   VOID\r
   );\r
 \r
-\r
 ///\r
 ///  ID Register Helper functions\r
 ///\r
@@ -768,6 +769,7 @@ ArmHasCcidx (
 ///\r
 /// AArch32-only ID Register Helper functions\r
 ///\r
+\r
 /**\r
   Check whether the CPU supports the Security extensions\r
 \r
@@ -779,6 +781,7 @@ EFIAPI
 ArmHasSecurityExtensions (\r
   VOID\r
   );\r
+\r
 #endif // MDE_CPU_ARM\r
 \r
 #endif // ARM_LIB_H_\r