\r
#include <Uefi/UefiBaseType.h>\r
\r
-#ifdef ARM_CPU_ARMv6\r
-#include <Chipset/ARM1176JZ-S.h>\r
+#ifdef MDE_CPU_ARM\r
+ #ifdef ARM_CPU_ARMv6\r
+ #include <Chipset/ARM1176JZ-S.h>\r
+ #else\r
+ #include <Chipset/ArmV7.h>\r
+ #endif\r
+#elif defined(MDE_CPU_AARCH64)\r
+ #include <Chipset/AArch64.h>\r
#else\r
-#include <Chipset/ArmV7.h>\r
+ #error "Unknown chipset."\r
#endif\r
\r
typedef enum {\r
//\r
// ARM MP Core IDs\r
//\r
-#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))\r
#define ARM_CORE_MASK 0xFF\r
#define ARM_CLUSTER_MASK (0xFF << 8)\r
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
// Get the position of the core for the Stack Offset (4 Core per Cluster)\r
// Position = (ClusterId * 4) + CoreId\r
#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r
ArmInstructionCacheLineLength (\r
VOID\r
);\r
- \r
+\r
+UINTN\r
+EFIAPI\r
+ArmIsArchTimerImplemented (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr0 (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr1 (\r
+ VOID\r
+ );\r
+\r
UINT32\r
EFIAPI\r
Cp15IdCode (\r
VOID\r
);\r
\r
-VOID\r
+RETURN_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
+ OUT VOID **TranslationTableBase OPTIONAL,\r
OUT UINTN *TranslationTableSize OPTIONAL\r
);\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
+\r
VOID\r
);\r
\r
VOID\r
);\r
\r
-UINT32\r
-EFIAPI\r
-ArmReadNsacr (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteNsacr (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
VOID\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmReadHVBar (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteHVBar (\r
+ IN UINTN HypModeVectorBase\r
+ );\r
+\r
#endif // __ARM_LIB__\r