-#define ARM_CORE_MASK 0xFF\r
-#define ARM_CLUSTER_MASK (0xFF << 8)\r
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
-// Get the position of the core for the Stack Offset (4 Core per Cluster)\r
-// Position = (ClusterId * 4) + CoreId\r
-#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
-\r
-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
- VOID\r
+#define ARM_CORE_AFF0 0xFF\r
+#define ARM_CORE_AFF1 (0xFF << 8)\r
+#define ARM_CORE_AFF2 (0xFF << 16)\r
+#define ARM_CORE_AFF3 (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
+#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)\r
+#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)\r
+#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)\r
+#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)\r
+#define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)\r
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
+#define MPIDR_MT_BIT BIT24\r
+\r
+/** Reads the CCSIDR register for the specified cache.\r
+\r
+ @param CSSELR The CSSELR cache selection register value.\r
+\r
+ @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
+ Returns the contents of the CCSIDR register in AARCH32 mode.\r
+**/\r
+UINTN\r
+ReadCCSIDR (\r
+ IN UINT32 CSSELR\r