\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
- Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
-#ifndef __ARM_LIB__\r
-#define __ARM_LIB__\r
+#ifndef ARM_LIB_H_\r
+#define ARM_LIB_H_\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
#include <Chipset/ArmV7.h>\r
-#elif defined(MDE_CPU_AARCH64)\r
+#elif defined (MDE_CPU_AARCH64)\r
#include <Chipset/AArch64.h>\r
#else\r
- #error "Unknown chipset."\r
+ #error "Unknown chipset."\r
#endif\r
\r
-#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
EFI_MEMORY_UCE)\r
\r
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
-#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
- EFI_PHYSICAL_ADDRESS PhysicalBase;\r
- EFI_VIRTUAL_ADDRESS VirtualBase;\r
- UINT64 Length;\r
- ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
+ EFI_PHYSICAL_ADDRESS PhysicalBase;\r
+ EFI_VIRTUAL_ADDRESS VirtualBase;\r
+ UINT64 Length;\r
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
-typedef VOID (*CACHE_OPERATION)(VOID);\r
-typedef VOID (*LINE_OPERATION)(UINTN);\r
+typedef VOID (*CACHE_OPERATION)(\r
+ VOID\r
+ );\r
+typedef VOID (*LINE_OPERATION)(\r
+ UINTN\r
+ );\r
\r
//\r
// ARM Processor Mode\r
//\r
// ARM Cpu IDs\r
//\r
-#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
-#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
-#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
-#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
-#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
-#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
-\r
-#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
+\r
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
-#define ARM_CORE_AFF0 0xFF\r
-#define ARM_CORE_AFF1 (0xFF << 8)\r
-#define ARM_CORE_AFF2 (0xFF << 16)\r
-#define ARM_CORE_AFF3 (0xFFULL << 32)\r
-\r
-#define ARM_CORE_MASK ARM_CORE_AFF0\r
-#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
-\r
-// The ARM Architecture Reference Manual for ARMv8-A defines up\r
-// to 7 levels of cache, L1 through L7.\r
-#define MAX_ARM_CACHE_LEVEL 7\r
+#define ARM_CORE_AFF0 0xFF\r
+#define ARM_CORE_AFF1 (0xFF << 8)\r
+#define ARM_CORE_AFF2 (0xFF << 16)\r
+#define ARM_CORE_AFF3 (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
+#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)\r
+#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)\r
+#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)\r
+#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)\r
+#define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)\r
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
+#define MPIDR_MT_BIT BIT24\r
+\r
+/** Reads the CCSIDR register for the specified cache.\r
+\r
+ @param CSSELR The CSSELR cache selection register value.\r
+\r
+ @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
+ Returns the contents of the CCSIDR register in AARCH32 mode.\r
+**/\r
+UINTN\r
+ReadCCSIDR (\r
+ IN UINT32 CSSELR\r
+ );\r
+\r
+/** Reads the CCSIDR2 for the specified cache.\r
+\r
+ @param CSSELR The CSSELR cache selection register value\r
+\r
+ @return The contents of the CCSIDR2 register for the specified cache.\r
+**/\r
+UINT32\r
+ReadCCSIDR2 (\r
+ IN UINT32 CSSELR\r
+ );\r
+\r
+/** Reads the Cache Level ID (CLIDR) register.\r
+\r
+ @return The contents of the CLIDR_EL1 register.\r
+**/\r
+UINT32\r
+ReadCLIDR (\r
+ VOID\r
+ );\r
\r
UINTN\r
EFIAPI\r
VOID\r
);\r
\r
-\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
-IN UINTN Address\r
-);\r
+ IN UINTN Address\r
+ );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
- IN VOID *TranslationTableEntry,\r
- IN VOID *Mva\r
+ IN VOID *TranslationTableEntry,\r
+ IN VOID *Mva\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
);\r
\r
VOID *\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
- IN UINTN VectorBase\r
+ IN UINTN VectorBase\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
- IN UINT32 Bit\r
+ IN UINT32 Bit\r
);\r
\r
UINT32\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
);\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
- IN UINT32 Access\r
+ IN UINT32 Access\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
);\r
\r
UINT32\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
- IN UINT32 VectorMonitorBase\r
+ IN UINT32 VectorMonitorBase\r
);\r
\r
UINT32\r
VOID\r
EFIAPI\r
ArmWriteSctlr (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
- IN UINTN HypModeVectorBase\r
+ IN UINTN HypModeVectorBase\r
);\r
\r
-\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
- IN UINTN Val\r
+ IN UINTN Val\r
);\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
- IN UINTN Bits\r
+ IN UINTN Bits\r
);\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
- IN UINTN Bits\r
+ IN UINTN Bits\r
);\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
-#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
-#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
-#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
+#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
\r
UINTN\r
EFIAPI\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
- UINTN FreqInHz\r
+ UINTN FreqInHz\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
- UINT64 Val\r
+ UINT64 Val\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
- UINT64 Val\r
+ UINT64 Val\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
- UINT64 Val\r
+ UINT64 Val\r
);\r
\r
UINTN\r
VOID\r
);\r
\r
-\r
///\r
/// ID Register Helper functions\r
///\r
VOID\r
);\r
\r
+/** Checks if CCIDX is implemented.\r
+\r
+ @retval TRUE CCIDX is implemented.\r
+ @retval FALSE CCIDX is not implemented.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArmHasCcidx (\r
+ VOID\r
+ );\r
+\r
#ifdef MDE_CPU_ARM\r
///\r
/// AArch32-only ID Register Helper functions\r
///\r
+\r
/**\r
Check whether the CPU supports the Security extensions\r
\r
ArmHasSecurityExtensions (\r
VOID\r
);\r
+\r
#endif // MDE_CPU_ARM\r
\r
-#endif // __ARM_LIB__\r
+#endif // ARM_LIB_H_\r
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