ArmPkg/ArmLib: Replaced 'UINTN' type by architecture agnostic types (EFI_PHYSICAL_ADD...

[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 468e663989234fb42a6e0750c60846492a1cbcd0..c8f0d94cad55cb666027ae058e57b2528653bfa8 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -15,6 +15,14 @@
 #ifndef __ARM_LIB__
 #define __ARM_LIB__
 
+#include <Uefi/UefiBaseType.h>
+
+#ifdef ARM_CPU_ARMv6
+#include <Chipset/ARM1176JZ-S.h>
+#else
+#include <Chipset/ArmV7.h>
+#endif
+
 typedef enum {
   ARM_CACHE_TYPE_WRITE_BACK,
   ARM_CACHE_TYPE_UNKNOWN
@@ -53,9 +61,9 @@ typedef enum {
 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
 
 typedef struct {
-  UINT32                        PhysicalBase;
-  UINT32                        VirtualBase;
-  UINT32                        Length;
+  EFI_PHYSICAL_ADDRESS          PhysicalBase;
+  EFI_VIRTUAL_ADDRESS           VirtualBase;
+  UINTN                         Length;
   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
 } ARM_MEMORY_REGION_DESCRIPTOR;
 
@@ -73,6 +81,14 @@ typedef enum {
   ARM_PROCESSOR_MODE_MASK       = 0x1F
 } ARM_PROCESSOR_MODE;
 
+#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
+#define GET_CORE_ID(MpId)     ((MpId) & 0x3)
+#define GET_CLUSTER_ID(MpId)  (((MpId) >> 8) & 0x3C)
+// Get the position of the core for the Stack Offset (4 Core per Cluster)
+//   Position = (ClusterId * 4) + CoreId
+#define GET_CORE_POS(MpId)    ((((MpId) >> 6) & 0x3C) + ((MpId) & 0x3))
+#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & 0x3)
+
 ARM_CACHE_TYPE
 EFIAPI
 ArmCacheType (
@@ -153,7 +169,7 @@ Cp15CacheInfo (
 
 BOOLEAN
 EFIAPI
-ArmIsMPCore (
+ArmIsMpCore (
   VOID
   );
 
@@ -176,6 +192,12 @@ ArmCleanDataCache (
   VOID
   );
 
+VOID
+EFIAPI
+ArmCleanDataCacheToPoU (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmInvalidateInstructionCache (
@@ -242,6 +264,12 @@ ArmDisableCachesAndMmu (
   VOID
   );
 
+VOID
+EFIAPI
+ArmInvalidateInstructionAndDataTlb (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmEnableInterrupts (
@@ -376,6 +404,77 @@ EFIAPI
 ArmInstructionSynchronizationBarrier (
   VOID
   );
-  
+
+VOID
+EFIAPI
+ArmWriteVBar (
+  IN  UINT32   VectorBase
+  );
+
+UINT32
+EFIAPI
+ArmReadVBar (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteAuxCr (
+  IN  UINT32    Bit
+  );
+
+UINT32
+EFIAPI
+ArmReadAuxCr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmSetAuxCrBit (
+  IN  UINT32    Bits
+  );
+
+VOID
+EFIAPI
+ArmCallWFI (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmReadMpidr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteCPACR (
+  IN  UINT32   Access
+  );
+
+VOID
+EFIAPI
+ArmEnableVFP (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteNsacr (
+  IN  UINT32   SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmWriteScr (
+  IN  UINT32   SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmWriteVMBar (
+  IN  UINT32   VectorMonitorBase
+  );
 
 #endif // __ARM_LIB__