ArmPkg/ArmLib: don't invalidate entire I-cache on range operation

[mirror_edk2.git] / ArmPkg / Library / ArmCacheMaintenanceLib / ArmCacheMaintenanceLib.c

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index 1045f9068f4dc0d71d71785d46f6dac4d053004c..0759e38cd4880798449b1d69e6c4eee1363936df 100644 (file)
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -17,15 +17,16 @@
 #include <Library/DebugLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
+STATIC\r
 VOID\r
 CacheRangeOperation (\r
   IN  VOID            *Start,\r
   IN  UINTN           Length,\r
-  IN  LINE_OPERATION  LineOperation\r
+  IN  LINE_OPERATION  LineOperation,\r
+  IN  UINTN           LineLength\r
   )\r
 {\r
-  UINTN ArmCacheLineLength         = ArmDataCacheLineLength();\r
-  UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;\r
+  UINTN ArmCacheLineAlignmentMask  = LineLength - 1;\r
 \r
   // Align address (rounding down)\r
   UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r
@@ -34,7 +35,7 @@ CacheRangeOperation (
   // Perform the line operation on an address in each cache line\r
   while (AlignedAddress < EndAddress) {\r
     LineOperation(AlignedAddress);\r
-    AlignedAddress += ArmCacheLineLength;\r
+    AlignedAddress += LineLength;\r
   }\r
   ArmDataSynchronizationBarrier ();\r
 }\r
@@ -64,8 +65,14 @@ InvalidateInstructionCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA);\r
-  ArmInvalidateInstructionCache ();\r
+  CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,\r
+    ArmDataCacheLineLength ());\r
+  CacheRangeOperation (Address, Length,\r
+    ArmInvalidateInstructionCacheEntryToPoUByMVA,\r
+    ArmInstructionCacheLineLength ());\r
+\r
+  ArmInstructionSynchronizationBarrier ();\r
+\r
   return Address;\r
 }\r
 \r
@@ -85,7 +92,8 @@ WriteBackInvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);\r
+  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,\r
+    ArmDataCacheLineLength ());\r
   return Address;\r
 }\r
 \r
@@ -105,7 +113,8 @@ WriteBackDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);\r
+  CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,\r
+    ArmDataCacheLineLength ());\r
   return Address;\r
 }\r
 \r
@@ -116,6 +125,7 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);\r
+  CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,\r
+    ArmDataCacheLineLength ());\r
   return Address;\r
 }\r