/** @file\r
- Default exception handler\r
+ Thumb Dissassembler. Still a work in progress.\r
+\r
+ Wrong output is a bug, so please fix it. \r
+ Hex output means there is not yet an entry or a decode bug.\r
+ gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit \r
+ 16-bit stream of Thumb2 instruction. Then there are big case \r
+ statements to print everything out. If you are adding instructions\r
+ try to reuse existing case entries if possible.\r
\r
Copyright (c) 2008-2010, Apple Inc. All rights reserved.\r
\r
\r
extern CHAR8 *gReg[];\r
\r
+// Thumb address modes\r
#define LOAD_STORE_FORMAT1 1\r
#define LOAD_STORE_FORMAT2 2\r
#define LOAD_STORE_FORMAT3 3\r
#define DATA_FORMAT8 19\r
#define CPS_FORMAT 20\r
#define ENDIAN_FORMAT 21\r
- \r
+#define DATA_CBZ 22\r
+#define ADR_FORMAT 23\r
+\r
+// Thumb2 address modes\r
#define B_T3 200\r
#define B_T4 201\r
#define BL_T2 202\r
+#define POP_T2 203\r
+#define POP_T3 204\r
+#define STM_FORMAT 205\r
+#define LDM_REG_IMM12_SIGNED 206\r
+#define LDM_REG_IMM12_LSL 207\r
+#define LDM_REG_IMM8 208\r
+#define LDM_REG_IMM12 209\r
+#define LDM_REG_INDIRECT_LSL 210\r
+#define LDM_REG_IMM8_SIGNED 211\r
+#define LDRD_REG_IMM8 212\r
+#define LDREXB 213\r
+#define LDREXD 214\r
+#define SRS_FORMAT 215\r
+#define RFE_FORMAT 216\r
+#define LDRD_REG_IMM8_SIGNED 217\r
+\r
+\r
\r
\r
typedef struct {\r
\r
THUMB_INSTRUCTIONS gOpThumb[] = {\r
// Thumb 16-bit instrucitons\r
-// Op Mask Format\r
+// Op Mask Format\r
{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },\r
-\r
+ { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>\r
{ "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },\r
{ "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },\r
{ "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },\r
\r
{ "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },\r
{ "BKPT", 0xdf00, 0xff00, IMMED_8 },\r
+ { "CBZ", 0xb100, 0xfd00, DATA_CBZ },\r
+ { "CBNZ", 0xb900, 0xfd00, DATA_CBZ },\r
{ "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },\r
\r
{ "CMP" , 0x2800, 0xf800, DATA_FORMAT3 },\r
{ "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },\r
{ "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },\r
{ "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }\r
+\r
};\r
\r
THUMB_INSTRUCTIONS gOpThumb2[] = {\r
- { "B", 0xf0008000, 0xf800d000, B_T3 },\r
- { "B", 0xf0009000, 0xf800d000, B_T4 },\r
- { "BL", 0xf000d000, 0xf800d000, B_T4 },\r
- { "BLX", 0xf000c000, 0xf800d000, BL_T2 }\r
- // ADD POP PUSH STR(B)(D) LDR(B)(D) EOR MOV ADDS SUBS STM\r
-#if 0 \r
+//Instruct OpCode OpCode Mask Addressig Mode\r
+ { "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>\r
+ { "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>\r
+ { "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>\r
+ { "BLX", 0xf000c000, 0xf800d000, BL_T2 }, // BLX<c> <label>\r
+\r
+ { "POP", 0xe8bd0000, 0xffff2000, POP_T2 }, // POP <registers>\r
+ { "POP", 0xf85d0b04, 0xffff0fff, POP_T3 }, // POP <register>\r
+ { "PUSH", 0xe8ad0000, 0xffffa000, POP_T2 }, // PUSH <registers>\r
+ { "PUSH", 0xf84d0d04, 0xffff0fff, POP_T3 }, // PUSH <register>\r
+ { "STM" , 0xe8800000, 0xffd0a000, STM_FORMAT }, // STM <Rn>{!},<registers>\r
+ { "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>\r
+ { "LDM" , 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>\r
+ { "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>\r
\r
- // 32-bit Thumb instructions op1 01\r
+ { "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}\r
+\r
+ { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label> \r
+ { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label> \r
+ { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label> \r
+ { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label> \r
+ { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label> \r
\r
- // 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple\r
- { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>\r
- { "SRS" , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT }, // SRS{IA}<c> SP{!},#<mode>\r
- { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}\r
- { "RFE" , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT }, // RFE{IA}<c> <Rn>{!}\r
- \r
- { "STM" , 0xe8800000, 0xffd00000, STM_FORMAT }, // STM<c>.W <Rn>{!},<registers>\r
- { "LDM" , 0xe8900000, 0xffd00000, STM_FORMAT }, // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]\r
- { "POP" , 0xe8bd0000, 0xffff2000, REGLIST_FORMAT }, // POP<c>.W <registers> >1 register\r
- { "POP" , 0xf85d0b04, 0xffff0fff, RT_FORMAT }, // POP<c>.W <registers> 1 register\r
+ { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+\r
+ { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRSB", 0xf9900800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form? \r
+ { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form? \r
+ { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]} \r
+ { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]} \r
+ { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]} \r
+\r
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>\r
+ \r
+ { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]] \r
+ { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>] \r
+ { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>] \r
+ \r
+ { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>] \r
\r
- { "STMDB", 0xe9000000, 0xffd00000, STM_FORMAT }, // STMDB\r
- { "PUSH" , 0xe8bd0000, 0xffffa000, REGLIST_FORMAT }, // PUSH<c>.W <registers> >1 register\r
- { "PUSH" , 0xf84d0b04, 0xffff0fff, RT_FORMAT }, // PUSH<c>.W <registers> 1 register\r
- { "LDMDB", 0xe9102000, 0xffd02000, STM_FORMAT }, // LDMDB<c> <Rn>{!},<registers>\r
+ { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]} \r
+ { "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}\r
+ { "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}\r
+ \r
+ { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
\r
- // 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,\r
- { "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT }, // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]\r
- { "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT }, // STREXB<c> <Rd>,<Rt>,[<Rn>]\r
- { "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT }, // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]\r
- { "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT }, // STREXH<c> <Rd>,<Rt>,[<Rn>]\r
- { "STRH", 0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT }, // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]\r
- { "STRH", 0xf8200000, 0xfff00000, }, // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]\r
+ { "STR", 0xf8400800, 0xfff00800, LDM_REG_IMM8 }, // STR <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]} \r
\r
+ { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
\r
+ { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]] \r
+ { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>] \r
+ { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>] \r
+ \r
+ { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>] \r
\r
- // 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing\r
- // 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor\r
- \r
- // 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate\r
- // 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate\r
- // 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches\r
- \r
- // 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item\r
- // 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store\r
- // 1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints \r
- // 1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints\r
- // 1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word \r
-\r
- // 1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register\r
- // 1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply\r
- // 1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply\r
- // 1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor \r
-#endif\r
+ { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>\r
+ { "SRS" , 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>\r
+ { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}\r
+ { "RFE" , 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}\r
};\r
\r
CHAR8 mThumbMregListStr[4*15 + 1];\r
UINT32 OpCode32;\r
UINT32 Index;\r
UINT32 Offset;\r
- UINT16 Rd, Rn, Rm;\r
+ UINT16 Rd, Rn, Rm, Rt, Rt2;\r
BOOLEAN H1, H2, imod;\r
UINT32 PC, Target;\r
CHAR8 *Cond;\r
- BOOLEAN S, J1, J2;\r
+ BOOLEAN S, J1, J2, P, U, W;\r
\r
OpCodePtr = *OpCodePtrPtr;\r
OpCode = **OpCodePtrPtr;\r
case LOAD_STORE_FORMAT3:\r
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PC + 2 + Target); \r
return;\r
case LOAD_STORE_FORMAT4:\r
// Rt, [SP, #imm8]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target, PC + 3 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target, PC + 2 + Target); \r
return;\r
\r
case LOAD_STORE_MULTIPLE_FORMAT1:\r
// A7.1.24\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE"); \r
return;\r
+\r
+ case DATA_CBZ:\r
+ // CB{N}Z <Rn>, <Lable>\r
+ Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target); \r
+ return;\r
+\r
+ case ADR_FORMAT:\r
+ // ADR <Rd>, <Label>\r
+ Target = (OpCode & 0xff) << 2;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PC + 4 + Target); \r
+ return;\r
}\r
}\r
}\r
\r
// Thumb2 are 32-bit instructions\r
*OpCodePtrPtr += 1;\r
+ Rt = (OpCode32 >> 12) & 0xf;\r
+ Rt2 = (OpCode32 >> 8) & 0xf;\r
+ Rm = (OpCode32 & 0xf);\r
+ Rn = (OpCode32 >> 16) & 0xf;\r
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {\r
if (Extended) {\r
Target = SignExtend32 (Target, BIT25);\r
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); \r
return;\r
+\r
+ case POP_T2:\r
+ // <reglist> some must be zero, handled in table\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList (OpCode32 & 0xffff));\r
+ return;\r
+\r
+ case POP_T3:\r
+ // <register> \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);\r
+ return;\r
+\r
+ case STM_FORMAT:\r
+ // <Rn>{!}, <registers>\r
+ W = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
+ return;\r
+\r
+ case LDM_REG_IMM12_SIGNED:\r
+ // <rt>, <label>\r
+ Target = OpCode32 & 0xfff; \r
+ if ((OpCode32 & BIT23) == 0) {\r
+ // U == 0 means subtrack, U == 1 means add\r
+ Target = -Target;\r
+ }\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PC + 4 + Target);\r
+ return;\r
+\r
+ case LDM_REG_INDIRECT_LSL:\r
+ // <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a, %a", gReg[Rt], gReg[Rn], gReg[Rm]);\r
+ if (((OpCode32 >> 4) && 3) == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) && 3);\r
+ }\r
+ return;\r
+ \r
+ case LDM_REG_IMM12:\r
+ // <rt>, [<rn>, {, #<imm12>]}\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
+ if ((OpCode32 && 0xfff) == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #0x%x]", OpCode32 & 0xfff);\r
+ }\r
+ return;\r
+\r
+ case LDM_REG_IMM8:\r
+ // <rt>, [<rn>, {, #<imm8>}]{!}\r
+ W = (OpCode32 & BIT8) == BIT8;\r
+ U = (OpCode32 & BIT9) == BIT9;\r
+ P = (OpCode32 & BIT10) == BIT10;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
+ if (P) {\r
+ if ((OpCode32 && 0xff) == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", OpCode32 & 0xff, U?"":"-" ,W?"!":"");\r
+ }\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x]%a", OpCode32 & 0xff, U?"":"-");\r
+ }\r
+ return;\r
+\r
+ case LDRD_REG_IMM8_SIGNED:\r
+ // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
+ P = (OpCode32 & BIT24) == BIT24; // index = P\r
+ U = (OpCode32 & BIT23) == BIT23; \r
+ W = (OpCode32 & BIT21) == BIT21;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
+ if (P) {\r
+ if ((OpCode32 && 0xff) == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");\r
+ }\r
+ } else {\r
+ if ((OpCode32 && 0xff) != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);\r
+ }\r
+ }\r
+ return;\r
+\r
+ case LDRD_REG_IMM8: \r
+ // LDRD <rt>, <rt2>, <label> \r
+ Target = (OpCode32 & 0xff) << 2; \r
+ if ((OpCode32 & BIT23) == 0) {\r
+ // U == 0 means subtrack, U == 1 means add\r
+ Target = -Target;\r
+ }\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);\r
+ return;\r
+\r
+ case LDREXB:\r
+ // LDREXB <Rt>, [Rn]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a]", gReg[Rt], gReg[Rn]);\r
+ return;\r
+\r
+ case LDREXD:\r
+ // LDREXD <Rt>, <Rt2>, [<Rn>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
+ return;\r
+ \r
+ case SRS_FORMAT:\r
+ // SP{!}, #<mode>\r
+ W = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);\r
+ return;\r
+\r
+ case RFE_FORMAT:\r
+ // <Rn>{!}\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");\r
+ return;\r
+\r
}\r
}\r
}\r
projects / mirror_edk2.git / blobdiff