// feature is implemented on the CPU. This is also convenient as our GICv3\r
// driver requires SRE. If only Memory mapped access is available we try to\r
// drive the GIC as a v2.\r
- if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {\r
+ if (ArmHasGicSystemRegisters ()) {\r
// Make sure System Register access is enabled (SRE). This depends on the\r
// higher privilege level giving us permission, otherwise we will either\r
// cause an exception here, or the write doesn't stick in which case we need\r