*\r
* Copyright (c) 2014, ARM Limited. All rights reserved.\r
*\r
-* This program and the accompanying materials are licensed and made available\r
-* under the terms and conditions of the BSD License which accompanies this\r
-* distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#include <Library/ArmLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
-ARM_GIC_ARCH_REVISION\r
+STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;\r
+\r
+RETURN_STATUS\r
EFIAPI\r
-ArmGicGetSupportedArchRevision (\r
+ArmGicArchLibInitialize (\r
VOID\r
)\r
{\r
// feature is implemented on the CPU. This is also convenient as our GICv3\r
// driver requires SRE. If only Memory mapped access is available we try to\r
// drive the GIC as a v2.\r
- if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {\r
+ if (ArmHasGicSystemRegisters ()) {\r
// Make sure System Register access is enabled (SRE). This depends on the\r
// higher privilege level giving us permission, otherwise we will either\r
// cause an exception here, or the write doesn't stick in which case we need\r
IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
}\r
if (IccSre & ICC_SRE_EL2_SRE) {\r
- return ARM_GIC_ARCH_REVISION_3;\r
+ mGicArchRevision = ARM_GIC_ARCH_REVISION_3;\r
+ goto Done;\r
}\r
}\r
\r
- return ARM_GIC_ARCH_REVISION_2;\r
+ mGicArchRevision = ARM_GIC_ARCH_REVISION_2;\r
+\r
+Done:\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+ VOID\r
+ )\r
+{\r
+ return mGicArchRevision;\r
}\r