ArmPkg: Added Aarch64 support

[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Lib.c

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
new file mode 100644 (file)
index 0000000..fd7f14f
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
@@ -0,0 +1,263 @@
+/** @file\r
+\r
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Chipset/AArch64.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include "AArch64Lib.h"\r
+#include "ArmLibPrivate.h"\r
+\r
+ARM_CACHE_TYPE\r
+EFIAPI\r
+ArmCacheType (\r
+  VOID\r
+  )\r
+{\r
+  return ARM_CACHE_TYPE_WRITE_BACK;\r
+}\r
+\r
+ARM_CACHE_ARCHITECTURE\r
+EFIAPI\r
+ArmCacheArchitecture (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CLIDR = ReadCLIDR ();\r
+\r
+  return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me\r
+}\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmDataCachePresent (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CLIDR = ReadCLIDR ();\r
+\r
+  if ((CLIDR & 0x2) == 0x2) {\r
+    // Instruction cache exists\r
+    return TRUE;\r
+  }\r
+  if ((CLIDR & 0x7) == 0x4) {\r
+    // Unified cache\r
+    return TRUE;\r
+  }\r
+\r
+  return FALSE;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDataCacheSize (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 NumSets;\r
+  UINT32 Associativity;\r
+  UINT32 LineSize;\r
+  UINT32 CCSIDR = ReadCCSIDR (0);\r
+\r
+  LineSize      = (1 << ((CCSIDR & 0x7) + 2));\r
+  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
+  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;\r
+\r
+  // LineSize is in words (4 byte chunks)\r
+  return  NumSets * Associativity * LineSize * 4;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDataCacheAssociativity (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CCSIDR = ReadCCSIDR (0);\r
+\r
+  return ((CCSIDR >> 3) & 0x3ff) + 1;\r
+}\r
+\r
+UINTN\r
+ArmDataCacheSets (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CCSIDR = ReadCCSIDR (0);\r
+\r
+  return ((CCSIDR >> 13) & 0x7fff) + 1;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r
+\r
+  // * 4 converts to bytes\r
+  return (1 << (CCSIDR + 2)) * 4;\r
+}\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmInstructionCachePresent (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CLIDR = ReadCLIDR ();\r
+\r
+  if ((CLIDR & 1) == 1) {\r
+    // Instruction cache exists\r
+    return TRUE;\r
+  }\r
+  if ((CLIDR & 0x7) == 0x4) {\r
+    // Unified cache\r
+    return TRUE;\r
+  }\r
+\r
+  return FALSE;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheSize (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 NumSets;\r
+  UINT32 Associativity;\r
+  UINT32 LineSize;\r
+  UINT32 CCSIDR = ReadCCSIDR (1);\r
+\r
+  LineSize      = (1 << ((CCSIDR & 0x7) + 2));\r
+  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
+  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;\r
+\r
+  // LineSize is in words (4 byte chunks)\r
+  return  NumSets * Associativity * LineSize * 4;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheAssociativity (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CCSIDR = ReadCCSIDR (1);\r
+\r
+  return ((CCSIDR >> 3) & 0x3ff) + 1;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheSets (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CCSIDR = ReadCCSIDR (1);\r
+\r
+  return ((CCSIDR >> 13) & 0x7fff) + 1;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r
+\r
+  // * 4 converts to bytes\r
+  return (1 << (CCSIDR + 2)) * 4;\r
+}\r
+\r
+\r
+VOID\r
+AArch64DataCacheOperation (\r
+  IN  AARCH64_CACHE_OPERATION  DataCacheOperation\r
+  )\r
+{\r
+  UINTN     SavedInterruptState;\r
+\r
+  SavedInterruptState = ArmGetInterruptState ();\r
+  ArmDisableInterrupts();\r
+\r
+  AArch64AllDataCachesOperation (DataCacheOperation);\r
+\r
+  ArmDrainWriteBuffer ();\r
+\r
+  if (SavedInterruptState) {\r
+    ArmEnableInterrupts ();\r
+  }\r
+}\r
+\r
+\r
+VOID\r
+AArch64PoUDataCacheOperation (\r
+  IN  AARCH64_CACHE_OPERATION  DataCacheOperation\r
+  )\r
+{\r
+  UINTN     SavedInterruptState;\r
+\r
+  SavedInterruptState = ArmGetInterruptState ();\r
+  ArmDisableInterrupts ();\r
+\r
+  AArch64PerformPoUDataCacheOperation (DataCacheOperation);\r
+\r
+  ArmDrainWriteBuffer ();\r
+\r
+  if (SavedInterruptState) {\r
+    ArmEnableInterrupts ();\r
+  }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCache (\r
+  VOID\r
+  )\r
+{\r
+  AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCache (\r
+  VOID\r
+  )\r
+{\r
+  AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCache (\r
+  VOID\r
+  )\r
+{\r
+  AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheToPoU (\r
+  VOID\r
+  )\r
+{\r
+  AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
+}\r