ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () alias

[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Support.S

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index a57e976979a8683ada8be8fbb19429f1ba911983..c530d19e897e3548fe28d3461d610c82f6cd268e 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -26,7 +26,6 @@ GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmDrainWriteBuffer)\r
 GCC_ASM_EXPORT (ArmEnableMmu)\r
 GCC_ASM_EXPORT (ArmDisableMmu)\r
 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r
@@ -40,15 +39,13 @@ GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
 GCC_ASM_EXPORT (ArmEnableBranchPrediction)\r
 GCC_ASM_EXPORT (ArmDisableBranchPrediction)\r
 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)\r
-GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)\r
 GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)\r
+GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
 GCC_ASM_EXPORT (ArmWriteVBar)\r
 GCC_ASM_EXPORT (ArmReadVBar)\r
 GCC_ASM_EXPORT (ArmEnableVFP)\r
 GCC_ASM_EXPORT (ArmCallWFI)\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
 GCC_ASM_EXPORT (ArmReadMpidr)\r
 GCC_ASM_EXPORT (ArmReadTpidrurw)\r
 GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
@@ -67,43 +64,31 @@ GCC_ASM_EXPORT (ArmReadCurrentEL)
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
   dc      ivac, x0    // Invalidate single data cache line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
   dc      cvac, x0    // Clean single data cache line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
   dc      civac, x0   // Clean and invalidate single data cache line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
   dc      isw, x0     // Invalidate this line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
   dc      cisw, x0    // Clean and Invalidate this line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
   dc      csw, x0     // Clean this line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
@@ -124,18 +109,20 @@ ASM_PFX(ArmEnableMmu):
 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: tlbi    vmalle1\r
+   dsb     nsh\r
    isb\r
    msr     sctlr_el1, x0       // Write back\r
    b       4f\r
 2: tlbi    alle2\r
+   dsb     nsh\r
    isb\r
    msr     sctlr_el2, x0       // Write back\r
    b       4f\r
 3: tlbi    alle3\r
+   dsb     nsh\r
    isb\r
    msr     sctlr_el3, x0       // Write back\r
-4: dsb     sy\r
-   isb\r
+4: isb\r
    ret\r
 \r
 \r
@@ -146,7 +133,7 @@ ASM_PFX(ArmDisableMmu):
 2: mrs     x0, sctlr_el2        // Read System Control Register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Read System Control Register EL3\r
-4: bic     x0, x0, #CTRL_M_BIT  // Clear MMU enable bit\r
+4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back\r
    tlbi    vmalle1\r
@@ -168,9 +155,8 @@ ASM_PFX(ArmDisableCachesAndMmu):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_M_BIT  // Disable MMU\r
-   bic     x0, x0, #CTRL_C_BIT  // Disable D Cache\r
-   bic     x0, x0, #CTRL_I_BIT  // Disable I Cache\r
+4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches\r
+   and     x0, x0, x1\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -219,7 +205,7 @@ ASM_PFX(ArmDisableDataCache):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_C_BIT  // Clear C bit\r
+4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -257,7 +243,7 @@ ASM_PFX(ArmDisableInstructionCache):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_I_BIT  // Clear I bit\r
+4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -291,7 +277,7 @@ ASM_PFX(ArmDisableAlignmentCheck):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_A_BIT  // Clear A (alignment check) bit\r
+4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -315,8 +301,8 @@ ASM_PFX(ArmDisableBranchPrediction):
 \r
 ASM_PFX(AArch64AllDataCachesOperation):\r
 // We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
-  str   x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+  str   x30, [sp, #-16]!\r
   mov   x1, x0                  // Save Function call in x1\r
   mrs   x6, clidr_el1           // Read EL1 CLIDR\r
   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)\r
@@ -324,19 +310,6 @@ ASM_PFX(AArch64AllDataCachesOperation):
                                 // right to ease the access to CSSELR and the Set/Way operation.\r
   cbz   x3, L_Finished          // No need to clean if LoC is 0\r
   mov   x10, #0                 // Start clean at cache level 0\r
-  b     Loop1\r
-\r
-ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
-// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
-  str   x30, [sp, #-0x10]!\r
-  mov   x1, x0                  // Save Function call in x1\r
-  mrs   x6, clidr_el1           // Read EL1 CLIDR\r
-  and   x3, x6, #0x38000000     // Mask out all but Point of Unification (PoU)\r
-  lsr   x3, x3, #26             // Left align cache level value - the level is shifted by 1 to the\r
-                                // right to ease the access to CSSELR and the Set/Way operation.\r
-  cbz   x3, L_Finished          // No need to clean if LoC is 0\r
-  mov   x10, #0                 // Start clean at cache level 0\r
 \r
 Loop1:\r
   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info\r
@@ -389,8 +362,7 @@ ASM_PFX(ArmDataMemoryBarrier):
   ret\r
 \r
 \r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
-ASM_PFX(ArmDrainWriteBuffer):\r
+ASM_PFX(ArmDataSynchronizationBarrier):\r
   dsb   sy\r
   ret\r
 \r
@@ -451,18 +423,6 @@ ASM_PFX(ArmCallWFI):
   ret\r
 \r
 \r
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
-   EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi  vmalle1\r
-   b     4f\r
-2: tlbi  alle2\r
-   b     4f\r
-3: tlbi  alle3\r
-4: dsb   sy\r
-   isb\r
-   ret\r
-\r
-\r
 ASM_PFX(ArmReadMpidr):\r
   mrs   x0, mpidr_el1           // read EL1 MPIDR\r
   ret\r