--- /dev/null
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+\r
+ INCLUDE AsmMacroExport.inc\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+ RVCT_ASM_EXPORT ArmIsMpCore\r
+ mrc p15,0,R0,c0,c0,5\r
+ // Get Multiprocessing extension (bit31) & U bit (bit30)\r
+ and R0, R0, #0xC0000000\r
+ // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r
+ cmp R0, #0x80000000\r
+ moveq R0, #1\r
+ movne R0, #0\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableAsynchronousAbort\r
+ cpsie a\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableAsynchronousAbort\r
+ cpsid a\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableIrq\r
+ cpsie i\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableIrq\r
+ cpsid i\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableFiq\r
+ cpsie f\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableFiq\r
+ cpsid f\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableInterrupts\r
+ cpsie if\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableInterrupts\r
+ cpsid if\r
+ isb\r
+ bx LR\r
+\r
+// UINT32\r
+// ReadCCSIDR (\r
+// IN UINT32 CSSELR\r
+// )\r
+ RVCT_ASM_EXPORT ReadCCSIDR\r
+ mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r
+ isb\r
+ mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r
+ bx lr\r
+\r
+// UINT32\r
+// ReadCLIDR (\r
+// IN UINT32 CSSELR\r
+// )\r
+ RVCT_ASM_EXPORT ReadCLIDR\r
+ mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadNsacr\r
+ mrc p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteNsacr\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ END\r