#ifndef ARM_V7_LIB_H_\r
#define ARM_V7_LIB_H_\r
\r
-#define ID_MMFR0_SHARELVL_SHIFT 12\r
-#define ID_MMFR0_SHARELVL_MASK 0xf\r
-#define ID_MMFR0_SHARELVL_ONE 0\r
-#define ID_MMFR0_SHARELVL_TWO 1\r
-\r
-#define ID_MMFR0_INNERSHR_SHIFT 28\r
-#define ID_MMFR0_INNERSHR_MASK 0xf\r
-#define ID_MMFR0_OUTERSHR_SHIFT 8\r
-#define ID_MMFR0_OUTERSHR_MASK 0xf\r
-\r
-#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
-#define ID_MMFR0_SHR_IGNORED 0xf\r
-\r
-typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);\r
+#define ID_MMFR0_SHARELVL_SHIFT 12\r
+#define ID_MMFR0_SHARELVL_MASK 0xf\r
+#define ID_MMFR0_SHARELVL_ONE 0\r
+#define ID_MMFR0_SHARELVL_TWO 1\r
+\r
+#define ID_MMFR0_INNERSHR_SHIFT 28\r
+#define ID_MMFR0_INNERSHR_MASK 0xf\r
+#define ID_MMFR0_OUTERSHR_SHIFT 8\r
+#define ID_MMFR0_OUTERSHR_MASK 0xf\r
+\r
+#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
+#define ID_MMFR0_SHR_IGNORED 0xf\r
+\r
+typedef VOID (*ARM_V7_CACHE_OPERATION)(\r
+ UINT32\r
+ );\r
\r
VOID\r
ArmV7AllDataCachesOperation (\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
- IN UINTN SetWayFormat\r
+ IN UINTN SetWayFormat\r
);\r
\r
/** Reads the ID_MMFR4 register.\r
);\r
\r
#endif // ARM_V7_LIB_H_\r
-\r