\r
**/\r
\r
-#ifndef __ARM_LIB_PRIVATE_H__\r
-#define __ARM_LIB_PRIVATE_H__\r
+#ifndef ARM_LIB_PRIVATE_H_\r
+#define ARM_LIB_PRIVATE_H_\r
\r
-#define CACHE_SIZE_4_KB (3UL)\r
-#define CACHE_SIZE_8_KB (4UL)\r
-#define CACHE_SIZE_16_KB (5UL)\r
-#define CACHE_SIZE_32_KB (6UL)\r
-#define CACHE_SIZE_64_KB (7UL)\r
-#define CACHE_SIZE_128_KB (8UL)\r
+#define CACHE_SIZE_4_KB (3UL)\r
+#define CACHE_SIZE_8_KB (4UL)\r
+#define CACHE_SIZE_16_KB (5UL)\r
+#define CACHE_SIZE_32_KB (6UL)\r
+#define CACHE_SIZE_64_KB (7UL)\r
+#define CACHE_SIZE_128_KB (8UL)\r
\r
#define CACHE_ASSOCIATIVITY_DIRECT (0UL)\r
#define CACHE_ASSOCIATIVITY_4_WAY (2UL)\r
#define CACHE_ASSOCIATIVITY_8_WAY (3UL)\r
\r
-#define CACHE_PRESENT (0UL)\r
-#define CACHE_NOT_PRESENT (1UL)\r
+#define CACHE_PRESENT (0UL)\r
+#define CACHE_NOT_PRESENT (1UL)\r
\r
#define CACHE_LINE_LENGTH_32_BYTES (2UL)\r
\r
#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)\r
#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)\r
\r
-#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r
-#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r
-\r
-#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
-\r
-#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-\r
-#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r
-#define CACHE_TYPE_WRITE_BACK (0x0EUL)\r
-\r
-#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r
-#define CACHE_ARCHITECTURE_UNIFIED (0UL)\r
-#define CACHE_ARCHITECTURE_SEPARATE (1UL)\r
-\r
-\r
-/// Defines the structure of the CSSELR (Cache Size Selection) register\r
-typedef union {\r
- struct {\r
- UINT32 InD :1; ///< Instruction not Data bit\r
- UINT32 Level :3; ///< Cache level (zero based)\r
- UINT32 TnD :1; ///< Allocation not Data bit\r
- UINT32 Reserved :27; ///< Reserved, RES0\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
-} CSSELR_DATA;\r
-\r
-/// The cache type values for the InD field of the CSSELR register\r
-typedef enum\r
-{\r
- /// Select the data or unified cache\r
- CsselrCacheTypeDataOrUnified = 0,\r
- /// Select the instruction cache\r
- CsselrCacheTypeInstruction,\r
- CsselrCacheTypeMax\r
-} CSSELR_CACHE_TYPE;\r
-\r
-/// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
-typedef union {\r
- struct {\r
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
- UINT64 Associativity :10; ///< Associativity - 1\r
- UINT64 NumSets :15; ///< Number of sets in the cache -1\r
- UINT64 Unknown :4; ///< Reserved, UNKNOWN\r
- UINT64 Reserved :32; ///< Reserved, RES0\r
- } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
- struct {\r
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
- UINT64 Associativity :21; ///< Associativity - 1\r
- UINT64 Reserved1 :8; ///< Reserved, RES0\r
- UINT64 NumSets :24; ///< Number of sets in the cache -1\r
- UINT64 Reserved2 :8; ///< Reserved, RES0\r
- } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
- struct {\r
- UINT64 LineSize : 3;\r
- UINT64 Associativity : 21;\r
- UINT64 Reserved : 8;\r
- UINT64 Unallocated : 32;\r
- } BitsCcidxAA32;\r
- UINT64 Data; ///< The entire 64-bit value\r
-} CCSIDR_DATA;\r
-\r
-/// Defines the structure of the AARCH32 CCSIDR2 register.\r
-typedef union {\r
- struct {\r
- UINT32 NumSets :24; ///< Number of sets in the cache - 1\r
- UINT32 Reserved :8; ///< Reserved, RES0\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
-} CCSIDR2_DATA;\r
-\r
-/** Defines the structure of the CLIDR (Cache Level ID) register.\r
- *\r
- * The lower 32 bits are the same for both AARCH32 and AARCH64\r
- * so we can use the same structure for both.\r
-**/\r
-typedef union {\r
- struct {\r
- UINT32 Ctype1 : 3; ///< Level 1 cache type\r
- UINT32 Ctype2 : 3; ///< Level 2 cache type\r
- UINT32 Ctype3 : 3; ///< Level 3 cache type\r
- UINT32 Ctype4 : 3; ///< Level 4 cache type\r
- UINT32 Ctype5 : 3; ///< Level 5 cache type\r
- UINT32 Ctype6 : 3; ///< Level 6 cache type\r
- UINT32 Ctype7 : 3; ///< Level 7 cache type\r
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r
- UINT32 LoC : 3; ///< Level of Coherency\r
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r
- UINT32 Icb : 3; ///< Inner Cache Boundary\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
-} CLIDR_DATA;\r
-\r
-/// The cache types reported in the CLIDR register.\r
-typedef enum {\r
- /// No cache is present\r
- ClidrCacheTypeNone = 0,\r
- /// There is only an instruction cache\r
- ClidrCacheTypeInstructionOnly,\r
- /// There is only a data cache\r
- ClidrCacheTypeDataOnly,\r
- /// There are separate data and instruction caches\r
- ClidrCacheTypeSeparate,\r
- /// There is a unified cache\r
- ClidrCacheTypeUnified,\r
- ClidrCacheTypeMax\r
-} CLIDR_CACHE_TYPE;\r
-\r
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
+#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r
+#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r
+\r
+#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
+\r
+#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+\r
+#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r
+#define CACHE_TYPE_WRITE_BACK (0x0EUL)\r
+\r
+#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r
+#define CACHE_ARCHITECTURE_UNIFIED (0UL)\r
+#define CACHE_ARCHITECTURE_SEPARATE (1UL)\r
\r
VOID\r
CPSRMaskInsert (\r
VOID\r
);\r
\r
-/** Reads the CCSIDR register for the specified cache.\r
-\r
- @param CSSELR The CSSELR cache selection register value.\r
-\r
- @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
- Returns the contents of the CCSIDR register in AARCH32 mode.\r
-**/\r
-UINTN\r
-ReadCCSIDR (\r
- IN UINT32 CSSELR\r
- );\r
-\r
-/** Reads the CCSIDR2 for the specified cache.\r
-\r
- @param CSSELR The CSSELR cache selection register value\r
-\r
- @return The contents of the CCSIDR2 register for the specified cache.\r
-**/\r
-UINT32\r
-ReadCCSIDR2 (\r
- IN UINT32 CSSELR\r
- );\r
-\r
-UINT32\r
-ReadCLIDR (\r
- VOID\r
- );\r
-\r
-#endif // __ARM_LIB_PRIVATE_H__\r
+#endif // ARM_LIB_PRIVATE_H_\r
projects / mirror_edk2.git / blobdiff