Update remaining ARM .S files with INTERWORK_FUNC macro. This is the 2nd half of...

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
index 57d27345285083beaaa6dac9c58086e35b9facb7..8ca37f0be0441540ffc9f01a60bf816e073eec65 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
@@ -1,8 +1,8 @@
 #------------------------------------------------------------------------------ 
 #
-# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 #
-# All rights reserved. This program and the accompanying materials
+# This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 # which accompanies this distribution.  The full text of the license may be found at
 # http://opensource.org/licenses/bsd-license.php
@@ -12,19 +12,43 @@
 #
 #------------------------------------------------------------------------------
 
-.text
-.align 2
 .globl ASM_PFX(Cp15IdCode)
+INTERWORK_FUNC(Cp15IdCode)
 .globl ASM_PFX(Cp15CacheInfo)
+INTERWORK_FUNC(Cp15CacheInfo)
 .globl ASM_PFX(ArmEnableInterrupts)
+INTERWORK_FUNC(ArmEnableInterrupts)
 .globl ASM_PFX(ArmDisableInterrupts)
+INTERWORK_FUNC(ArmDisableInterrupts)
 .globl ASM_PFX(ArmGetInterruptState)
+INTERWORK_FUNC(ArmGetInterruptState)
+.globl ASM_PFX(ArmEnableFiq)
+INTERWORK_FUNC(ArmEnableFiq)
+.globl ASM_PFX(ArmDisableFiq)
+INTERWORK_FUNC(ArmDisableFiq)
+.globl ASM_PFX(ArmGetFiqState)
+INTERWORK_FUNC(ArmGetFiqState)
 .globl ASM_PFX(ArmInvalidateTlb)
+INTERWORK_FUNC(ArmInvalidateTlb)
 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
+INTERWORK_FUNC(ArmSetTranslationTableBaseAddress)
 .globl ASM_PFX(ArmGetTranslationTableBaseAddress)
+INTERWORK_FUNC(ArmGetTranslationTableBaseAddress)
 .globl ASM_PFX(ArmSetDomainAccessControl)
+INTERWORK_FUNC(ArmSetDomainAccessControl)
+.globl ASM_PFX(ArmUpdateTranslationTableEntry)
+INTERWORK_FUNC(ArmUpdateTranslationTableEntry)
 .globl ASM_PFX(CPSRMaskInsert)
+INTERWORK_FUNC(CPSRMaskInsert)
 .globl ASM_PFX(CPSRRead)
+INTERWORK_FUNC(CPSRRead)
+.globl ASM_PFX(ReadCCSIDR)
+INTERWORK_FUNC(ReadCCSIDR)
+.globl ASM_PFX(ReadCLIDR)
+INTERWORK_FUNC(ReadCLIDR)
+
+.text
+.align 2
 
 #------------------------------------------------------------------------------
 
@@ -37,18 +61,11 @@ ASM_PFX(Cp15CacheInfo):
   bx      LR
 
 ASM_PFX(ArmEnableInterrupts):
-       mrs     R0,CPSR
-       bic     R0,R0,#0x80             @Enable IRQ interrupts
-       msr     CPSR_c,R0
+  cpsie   i
        bx      LR
 
 ASM_PFX(ArmDisableInterrupts):
-       mrs     R0,CPSR
-       orr     R1,R0,#0x80             @Disable IRQ interrupts
-       msr     CPSR_c,R1
-  tst     R0,#0x80
-  moveq   R0,#1
-  movne   R0,#0
+  cpsid   i
        bx      LR
 
 ASM_PFX(ArmGetInterruptState):
@@ -58,22 +75,58 @@ ASM_PFX(ArmGetInterruptState):
        movne   R0,#0
        bx      LR
 
+ASM_PFX(ArmEnableFiq):
+  cpsie   f
+       bx      LR
+
+ASM_PFX(ArmDisableFiq):
+  cpsid   f
+       bx      LR
+
+ASM_PFX(ArmGetFiqState):
+       mrs     R0,CPSR
+       tst     R0,#0x40            @Check if FIQ is enabled.
+       moveq   R0,#1
+       movne   R0,#0
+       bx      LR
+
 ASM_PFX(ArmInvalidateTlb):
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0
+  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb
+  isb
   bx      lr
 
 ASM_PFX(ArmSetTranslationTableBaseAddress):
   mcr     p15,0,r0,c2,c0,0
+  isb
   bx      lr
 
 ASM_PFX(ArmGetTranslationTableBaseAddress):
   mrc     p15,0,r0,c2,c0,0
+  isb
   bx      lr
 
 
 ASM_PFX(ArmSetDomainAccessControl):
   mcr     p15,0,r0,c3,c0,0
+  isb
+  bx      lr
+
+//
+//VOID
+//ArmUpdateTranslationTableEntry (
+//  IN VOID  *TranslationTableEntry  // R0
+//  IN VOID  *MVA                    // R1
+//  );
+ASM_PFX(ArmUpdateTranslationTableEntry):
+  mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
+  dsb
+  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA  
+  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb
+  isb
   bx      lr
 
 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
@@ -84,6 +137,7 @@ ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to in
   and     r1, r1, r0        @ clear bits outside the mask in the input
   orr     r2, r2, r1        @ set field
   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
+  isb
   mov     sp, r3            @ restore stack pointer
   ldmfd   sp!, {r4-r12, lr} @ restore registers
   bx      lr                @ return (hopefully thumb-safe!)
@@ -92,4 +146,22 @@ ASM_PFX(CPSRRead):
   mrs     r0, cpsr
   bx      lr
   
+// UINT32 
+// ReadCCSIDR (
+//   IN UINT32 CSSELR
+//   )  
+ASM_PFX(ReadCCSIDR):
+  mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
+  isb
+  mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
+  bx  lr
+  
+// UINT32 
+// ReadCLIDR (
+//   IN UINT32 CSSELR
+//   )  
+ASM_PFX(ReadCLIDR):
+  mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
+  bx  lr
+
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED