Added FIQ interrupt primatives. Update exception handler to disable/reenable FIQ...

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
index fac928af362d3de3b725aee73a354e03b949309d..cdfd3dc9cf4cd3bd92d13970fea8b093a6a067a5 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
@@ -19,6 +19,9 @@
 .globl ASM_PFX(ArmEnableInterrupts)
 .globl ASM_PFX(ArmDisableInterrupts)
 .globl ASM_PFX(ArmGetInterruptState)
+.globl ASM_PFX(ArmEnableFiq)
+.globl ASM_PFX(ArmDisableFiq)
+.globl ASM_PFX(ArmGetFiqState)
 .globl ASM_PFX(ArmInvalidateTlb)
 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
 .globl ASM_PFX(ArmGetTranslationTableBaseAddress)
@@ -54,6 +57,21 @@ ASM_PFX(ArmGetInterruptState):
        movne   R0,#0
        bx      LR
 
+ASM_PFX(ArmEnableFiq):
+  cpsie   f
+       bx      LR
+
+ASM_PFX(ArmDisableFiq):
+  cpsid   f
+       bx      LR
+
+ASM_PFX(ArmGetFiqState):
+       mrs     R0,CPSR
+       tst     R0,#0x30            @Check if IRQ is enabled.
+       moveq   R0,#1
+       movne   R0,#0
+       bx      LR
+
 ASM_PFX(ArmInvalidateTlb):
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0