Added FIQ interrupt primatives. Update exception handler to disable/reenable FIQ...

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmLibSupport.asm

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
index 5d3083457ea698b7a2b35f5f48a01f157cbca702..65b3683f2670a916ddb8fe40253ec37593eec1b6 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
@@ -18,6 +18,9 @@
     EXPORT  ArmEnableInterrupts
     EXPORT  ArmDisableInterrupts
     EXPORT  ArmGetInterruptState
+    EXPORT  ArmEnableFiq
+    EXPORT  ArmDisableFiq
+    EXPORT  ArmGetFiqState
     EXPORT  ArmInvalidateTlb
     EXPORT  ArmSetTranslationTableBaseAddress
     EXPORT  ArmGetTranslationTableBaseAddress
@@ -25,7 +28,8 @@
     EXPORT  CPSRMaskInsert
     EXPORT  CPSRRead
     EXPORT  ReadCCSIDR
-
+    EXPORT  ReadCLIDR
+    
     AREA ArmLibSupport, CODE, READONLY
 
 Cp15IdCode
@@ -50,6 +54,21 @@ ArmGetInterruptState
        moveq   R0,#1
        movne   R0,#0
        bx      LR
+       
+ArmEnableFiq
+  CPSIE   f
+       bx      LR
+
+ArmDisableFiq
+  CPSID   f
+       bx      LR
+
+ArmGetFiqState
+       mrs     R0,CPSR
+       tst     R0,#0x40            ;Check if IRQ is enabled.
+       moveq   R0,#1
+       movne   R0,#0
+       bx      LR
   
 ArmInvalidateTlb
   mov     r0,#0
@@ -97,7 +116,7 @@ CPSRRead
 ReadCCSIDR
   MCR p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
   ISB
-  MRC p15,1,<Rt>,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
+  MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
   BX  lr
   
 
@@ -106,7 +125,7 @@ ReadCCSIDR
 //   IN UINT32 CSSELR
 //   )  
 ReadCLIDR
-  MRC p15,1,<Rt>,c0,c0,1 ; Read CP15 Cache Level ID Register
+  MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
   END