Added FIQ interrupt primatives. Update exception handler to disable/reenable FIQ...

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmLibSupport.asm

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
index cf5173997cebcbd27a2a11e62abdaf2cbc28b0bb..65b3683f2670a916ddb8fe40253ec37593eec1b6 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
@@ -18,101 +18,80 @@
     EXPORT  ArmEnableInterrupts
     EXPORT  ArmDisableInterrupts
     EXPORT  ArmGetInterruptState
+    EXPORT  ArmEnableFiq
+    EXPORT  ArmDisableFiq
+    EXPORT  ArmGetFiqState
     EXPORT  ArmInvalidateTlb
     EXPORT  ArmSetTranslationTableBaseAddress
     EXPORT  ArmGetTranslationTableBaseAddress
     EXPORT  ArmSetDomainAccessControl
     EXPORT  CPSRMaskInsert
     EXPORT  CPSRRead
-
+    EXPORT  ReadCCSIDR
+    EXPORT  ReadCLIDR
+    
     AREA ArmLibSupport, CODE, READONLY
 
 Cp15IdCode
-  DSB
-  ISB
   mrc     p15,0,R0,c0,c0,0
-  DSB
-  ISB
   bx      LR
 
 Cp15CacheInfo
-  DSB
-  ISB
   mrc     p15,0,R0,c0,c0,1
-  DSB
-  ISB
   bx      LR
 
 ArmEnableInterrupts
-  DSB
-  ISB
-       mrs     R0,CPSR
-       bic     R0,R0,#0x80             ;Enable IRQ interrupts
-       msr     CPSR_c,R0
-  DSB
-  ISB
+  CPSIE   i
        bx      LR
 
 ArmDisableInterrupts
-  DSB
-  ISB
-       mrs     R0,CPSR
-       orr     R1,R0,#0x80             ;Disable IRQ interrupts
-       msr     CPSR_c,R1
-  tst     R0,#0x80
-  moveq   R0,#1
-  movne   R0,#0
-  DSB
-  ISB
+  CPSID   i
        bx      LR
 
 ArmGetInterruptState
-  DSB
-  ISB
        mrs     R0,CPSR
        tst     R0,#0x80            ;Check if IRQ is enabled.
        moveq   R0,#1
        movne   R0,#0
-  DSB
-  ISB
+       bx      LR
+       
+ArmEnableFiq
+  CPSIE   f
+       bx      LR
+
+ArmDisableFiq
+  CPSID   f
+       bx      LR
+
+ArmGetFiqState
+       mrs     R0,CPSR
+       tst     R0,#0x40            ;Check if IRQ is enabled.
+       moveq   R0,#1
+       movne   R0,#0
        bx      LR
   
 ArmInvalidateTlb
-  DSB
-  ISB
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0
-  DSB
   ISB
   bx      lr
 
 ArmSetTranslationTableBaseAddress
-  DSB
-  ISB
   mcr     p15,0,r0,c2,c0,0
-  DSB
   ISB
   bx      lr
 
 ArmGetTranslationTableBaseAddress
-  DSB
-  ISB
   mrc     p15,0,r0,c2,c0,0
-  DSB
   ISB
   bx      lr
 
 ArmSetDomainAccessControl
-  DSB
-  ISB
   mcr     p15,0,r0,c3,c0,0
-  DSB
   ISB
   bx      lr
 
 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
-  DSB
-  ISB
   stmfd   sp!, {r4-r12, lr} ; save all the banked registers
   mov     r3, sp            ; copy the stack pointer into a non-banked register
   mrs     r2, cpsr          ; read the cpsr
@@ -120,20 +99,33 @@ CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to in
   and     r1, r1, r0        ; clear bits outside the mask in the input
   orr     r2, r2, r1        ; set field
   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
+  ISB
   mov     sp, r3            ; restore stack pointer
   ldmfd   sp!, {r4-r12, lr} ; restore registers
-  DSB
-  ISB
   bx      lr                ; return (hopefully thumb-safe!)
 
 CPSRRead
-  DSB
-  ISB
   mrs     r0, cpsr
-  DSB
-  ISB
   bx      lr
   
+
+// UINT32 
+// ReadCCSIDR (
+//   IN UINT32 CSSELR
+//   )  
+ReadCCSIDR
+  MCR p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
+  ISB
+  MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
+  BX  lr
+  
+
+// UINT32 
+// ReadCLIDR (
+//   IN UINT32 CSSELR
+//   )  
+ReadCLIDR
+  MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
   END