-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
.align 2\r
\r
GCC_ASM_EXPORT(ArmIsMpCore)\r
+GCC_ASM_EXPORT(ArmHasMpExtensions)\r
GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)\r
GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)\r
GCC_ASM_EXPORT(ArmEnableIrq)\r
GCC_ASM_EXPORT(ArmDisableInterrupts)\r
GCC_ASM_EXPORT(ReadCCSIDR)\r
GCC_ASM_EXPORT(ReadCLIDR)\r
+GCC_ASM_EXPORT(ArmReadNsacr)\r
+GCC_ASM_EXPORT(ArmWriteNsacr)\r
\r
#------------------------------------------------------------------------------\r
\r
mrc p15,0,R0,c0,c0,5\r
// Get Multiprocessing extension (bit31) & U bit (bit30)\r
and R0, R0, #0xC0000000\r
- // if bit30 == 0 then the processor is part of a multiprocessor system)\r
- and R0, R0, #0x80000000\r
+ // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r
+ cmp R0, #0x80000000\r
+ moveq R0, #1\r
+ movne R0, #0\r
bx LR\r
\r
ASM_PFX(ArmEnableAsynchronousAbort):\r
cpsid if\r
isb\r
bx LR\r
- \r
-// UINT32 \r
+\r
+// UINT32\r
// ReadCCSIDR (\r
// IN UINT32 CSSELR\r
-// ) \r
+// )\r
ASM_PFX(ReadCCSIDR):\r
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r
isb\r
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r
bx lr\r
- \r
-// UINT32 \r
+\r
+// UINT32\r
// ReadCLIDR (\r
// IN UINT32 CSSELR\r
-// ) \r
+// )\r
ASM_PFX(ReadCLIDR):\r
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r
bx lr\r
\r
+ASM_PFX(ArmReadNsacr):\r
+ mrc p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteNsacr):\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r