ArmPkg/ArmBaseLib: remove MemoryAllocationLib.h includes

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmLibSupportV7.S

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
index d9e3c86b690748b6e0db01878de52917218584a8..3939bbc6b66d34803c9f37a9151b5deb6afb7fb5 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
@@ -2,6 +2,7 @@
 #\r
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
 #\r
 # This program and the accompanying materials\r
 # are licensed and made available under the terms and conditions of the BSD License\r
@@ -15,27 +16,7 @@
 \r
 #include <AsmMacroIoLib.h>\r
 \r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmIsMpCore)\r
-GCC_ASM_EXPORT(ArmHasMpExtensions)\r
-GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)\r
-GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)\r
-GCC_ASM_EXPORT(ArmEnableIrq)\r
-GCC_ASM_EXPORT(ArmDisableIrq)\r
-GCC_ASM_EXPORT(ArmEnableFiq)\r
-GCC_ASM_EXPORT(ArmDisableFiq)\r
-GCC_ASM_EXPORT(ArmEnableInterrupts)\r
-GCC_ASM_EXPORT(ArmDisableInterrupts)\r
-GCC_ASM_EXPORT(ReadCCSIDR)\r
-GCC_ASM_EXPORT(ReadCLIDR)\r
-GCC_ASM_EXPORT(ArmReadNsacr)\r
-GCC_ASM_EXPORT(ArmWriteNsacr)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_PFX(ArmIsMpCore):\r
+ASM_FUNC(ArmIsMpCore)\r
   mrc     p15,0,R0,c0,c0,5\r
   // Get Multiprocessing extension (bit31) & U bit (bit30)\r
   and     R0, R0, #0xC0000000\r
@@ -45,48 +26,42 @@ ASM_PFX(ArmIsMpCore):
   movne   R0, #0\r
   bx      LR\r
 \r
-ASM_PFX(ArmHasMpExtensions):\r
-  mrc     p15,0,R0,c0,c0,5\r
-  // Get Multiprocessing extension (bit31)\r
-  lsr     R0, R0, #31\r
-  bx      LR\r
-\r
-ASM_PFX(ArmEnableAsynchronousAbort):\r
+ASM_FUNC(ArmEnableAsynchronousAbort)\r
   cpsie   a\r
   isb\r
   bx      LR\r
 \r
-ASM_PFX(ArmDisableAsynchronousAbort):\r
+ASM_FUNC(ArmDisableAsynchronousAbort)\r
   cpsid   a\r
   isb\r
   bx      LR\r
 \r
-ASM_PFX(ArmEnableIrq):\r
+ASM_FUNC(ArmEnableIrq)\r
   cpsie   i\r
   isb\r
   bx      LR\r
 \r
-ASM_PFX(ArmDisableIrq):\r
+ASM_FUNC(ArmDisableIrq)\r
   cpsid   i\r
   isb\r
   bx      LR\r
 \r
-ASM_PFX(ArmEnableFiq):\r
+ASM_FUNC(ArmEnableFiq)\r
   cpsie   f\r
   isb\r
   bx      LR\r
 \r
-ASM_PFX(ArmDisableFiq):\r
+ASM_FUNC(ArmDisableFiq)\r
   cpsid   f\r
   isb\r
   bx      LR\r
 \r
-ASM_PFX(ArmEnableInterrupts):\r
+ASM_FUNC(ArmEnableInterrupts)\r
   cpsie   if\r
   isb\r
   bx      LR\r
 \r
-ASM_PFX(ArmDisableInterrupts):\r
+ASM_FUNC(ArmDisableInterrupts)\r
   cpsid   if\r
   isb\r
   bx      LR\r
@@ -95,7 +70,7 @@ ASM_PFX(ArmDisableInterrupts):
 // ReadCCSIDR (\r
 //   IN UINT32 CSSELR\r
 //   )\r
-ASM_PFX(ReadCCSIDR):\r
+ASM_FUNC(ReadCCSIDR)\r
   mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)\r
   isb\r
   mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)\r
@@ -105,15 +80,15 @@ ASM_PFX(ReadCCSIDR):
 // ReadCLIDR (\r
 //   IN UINT32 CSSELR\r
 //   )\r
-ASM_PFX(ReadCLIDR):\r
+ASM_FUNC(ReadCLIDR)\r
   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r
   bx  lr\r
 \r
-ASM_PFX(ArmReadNsacr):\r
+ASM_FUNC(ArmReadNsacr)\r
   mrc     p15, 0, r0, c1, c1, 2\r
   bx      lr\r
 \r
-ASM_PFX(ArmWriteNsacr):\r
+ASM_FUNC(ArmWriteNsacr)\r
   mcr     p15, 0, r0, c1, c1, 2\r
   bx      lr\r
 \r