#include <Chipset/ArmV7.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
-VOID
-FillTranslationTable (
- IN UINT32 *TranslationTable,
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
- )
-{
- UINT32 *Entry;
- UINTN Sections;
- UINTN Index;
- UINT32 Attributes;
- UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
-
- switch (MemoryRegion->Attributes) {
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- default:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
- break;
- }
-
- Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
- Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
-
- for (Index = 0; Index < Sections; Index++) {
- *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
- PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
- }
-}
-
-VOID
-EFIAPI
-ArmConfigureMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
- OUT UINTN *TranslationTableSize OPTIONAL
- )
-{
- VOID *TranslationTable;
-
- // Allocate pages for translation table.
- TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
- TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
-
- if (TranslationTableBase != NULL) {
- *TranslationTableBase = TranslationTable;
- }
-
- if (TranslationTableBase != NULL) {
- *TranslationTableSize = TRANSLATION_TABLE_SIZE;
- }
-
- ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
-
- ArmCleanInvalidateDataCache();
- ArmInvalidateInstructionCache();
- ArmInvalidateTlb();
-
- ArmDisableDataCache();
- ArmDisableInstructionCache();
- ArmDisableMmu();
-
- // Make sure nothing sneaked into the cache
- ArmCleanInvalidateDataCache();
- ArmInvalidateInstructionCache();
-
- while (MemoryTable->Length != 0) {
- FillTranslationTable(TranslationTable, MemoryTable);
- MemoryTable++;
- }
-
- ArmSetTranslationTableBaseAddress(TranslationTable);
-
- ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
- DOMAIN_ACCESS_CONTROL_NONE(14) |
- DOMAIN_ACCESS_CONTROL_NONE(13) |
- DOMAIN_ACCESS_CONTROL_NONE(12) |
- DOMAIN_ACCESS_CONTROL_NONE(11) |
- DOMAIN_ACCESS_CONTROL_NONE(10) |
- DOMAIN_ACCESS_CONTROL_NONE( 9) |
- DOMAIN_ACCESS_CONTROL_NONE( 8) |
- DOMAIN_ACCESS_CONTROL_NONE( 7) |
- DOMAIN_ACCESS_CONTROL_NONE( 6) |
- DOMAIN_ACCESS_CONTROL_NONE( 5) |
- DOMAIN_ACCESS_CONTROL_NONE( 4) |
- DOMAIN_ACCESS_CONTROL_NONE( 3) |
- DOMAIN_ACCESS_CONTROL_NONE( 2) |
- DOMAIN_ACCESS_CONTROL_NONE( 1) |
- DOMAIN_ACCESS_CONTROL_MANAGER(0));
-
- ArmEnableInstructionCache();
- ArmEnableDataCache();
- ArmEnableMmu();
-}
-
ARM_CACHE_TYPE
EFIAPI
ArmCacheType (
{
UINT32 CLIDR = ReadCLIDR ();
- return CLIDR; // BugBug Fix Me
+ return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
}
BOOLEAN
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (0);
- LineSize = (1 << (CCSIDR + 2));
+ LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (1);
- LineSize = (1 << (CCSIDR + 2));
+ LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
+ ArmDisableInterrupts();
+
ArmV7AllDataCachesOperation (DataCacheOperation);
{
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
+
+VOID
+EFIAPI
+ArmSetAuxCrBit (
+ IN UINT32 Bits
+ )
+{
+ UINT32 val = ArmReadAuxCr();
+ val |= Bits;
+ ArmWriteAuxCr(val);
+}