ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () alias

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Lib.c

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
index 6a8f0d3fdd984b8a8fd5e1cb0ab219ed81d60546..23a7f2f2bb235106deed74873794e31e418eb4e9 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
@@ -20,175 +20,6 @@
 #include "ArmV7Lib.h"\r
 #include "ArmLibPrivate.h"\r
 \r
-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
-  VOID\r
-  )\r
-{\r
-  return ARM_CACHE_TYPE_WRITE_BACK;\r
-}\r
-\r
-ARM_CACHE_ARCHITECTURE\r
-EFIAPI\r
-ArmCacheArchitecture (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CLIDR = ReadCLIDR ();\r
-\r
-  return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me\r
-}\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmDataCachePresent (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CLIDR = ReadCLIDR ();\r
-\r
-  if ((CLIDR & 0x2) == 0x2) {\r
-    // Instruction cache exists\r
-    return TRUE;\r
-  }\r
-  if ((CLIDR & 0x7) == 0x4) {\r
-    // Unified cache\r
-    return TRUE;\r
-  }\r
-\r
-  return FALSE;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheSize (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 NumSets;\r
-  UINT32 Associativity;\r
-  UINT32 LineSize;\r
-  UINT32 CCSIDR = ReadCCSIDR (0);\r
-\r
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));\r
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;\r
-\r
-  // LineSize is in words (4 byte chunks)\r
-  return  NumSets * Associativity * LineSize * 4;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheAssociativity (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (0);\r
-\r
-  return ((CCSIDR >> 3) & 0x3ff) + 1;\r
-}\r
-\r
-UINTN\r
-ArmDataCacheSets (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (0);\r
-\r
-  return ((CCSIDR >> 13) & 0x7fff) + 1;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheLineLength (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r
-\r
-  // * 4 converts to bytes\r
-  return (1 << (CCSIDR + 2)) * 4;\r
-}\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmInstructionCachePresent (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CLIDR = ReadCLIDR ();\r
-\r
-  if ((CLIDR & 1) == 1) {\r
-    // Instruction cache exists\r
-    return TRUE;\r
-  }\r
-  if ((CLIDR & 0x7) == 0x4) {\r
-    // Unified cache\r
-    return TRUE;\r
-  }\r
-\r
-  return FALSE;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheSize (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 NumSets;\r
-  UINT32 Associativity;\r
-  UINT32 LineSize;\r
-  UINT32 CCSIDR = ReadCCSIDR (1);\r
-\r
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));\r
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;\r
-\r
-  // LineSize is in words (4 byte chunks)\r
-  return  NumSets * Associativity * LineSize * 4;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheAssociativity (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (1);\r
-\r
-  return ((CCSIDR >> 3) & 0x3ff) + 1;\r
-//  return 4;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheSets (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (1);\r
-\r
-  return ((CCSIDR >> 13) & 0x7fff) + 1;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheLineLength (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r
-\r
-  // * 4 converts to bytes\r
-  return (1 << (CCSIDR + 2)) * 4;\r
-\r
-//  return 64;\r
-}\r
-\r
-\r
 VOID\r
 ArmV7DataCacheOperation (\r
   IN  ARM_V7_CACHE_OPERATION  DataCacheOperation\r
@@ -201,7 +32,7 @@ ArmV7DataCacheOperation (
 \r
   ArmV7AllDataCachesOperation (DataCacheOperation);\r
 \r
-  ArmDrainWriteBuffer ();\r
+  ArmDataSynchronizationBarrier ();\r
 \r
   if (SavedInterruptState) {\r
     ArmEnableInterrupts ();\r
@@ -214,7 +45,7 @@ ArmInvalidateDataCache (
   VOID\r
   )\r
 {\r
-  ArmDrainWriteBuffer ();\r
+  ArmDataSynchronizationBarrier ();\r
   ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r
 }\r
 \r
@@ -224,7 +55,7 @@ ArmCleanInvalidateDataCache (
   VOID\r
   )\r
 {\r
-  ArmDrainWriteBuffer ();\r
+  ArmDataSynchronizationBarrier ();\r
   ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r
 }\r
 \r
@@ -234,6 +65,6 @@ ArmCleanDataCache (
   VOID\r
   )\r
 {\r
-  ArmDrainWriteBuffer ();\r
+  ArmDataSynchronizationBarrier ();\r
   ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
 }\r