-/** @file
-
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-#include <Uefi.h>
-#include <Chipset/ArmV7.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include "ArmV7Lib.h"
-#include "ArmLibPrivate.h"
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
- )
-{
- return ARM_CACHE_TYPE_WRITE_BACK;
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
- VOID
- )
-{
- UINT32 CLIDR = ReadCLIDR ();
-
- return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- )
-{
- UINT32 CLIDR = ReadCLIDR ();
-
- if ((CLIDR & 0x2) == 0x2) {
- // Instruction cache exists
- return TRUE;
- }
- if ((CLIDR & 0x7) == 0x4) {
- // Unified cache
- return TRUE;
- }
-
- return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
- VOID
- )
-{
- UINT32 NumSets;
- UINT32 Associativity;
- UINT32 LineSize;
- UINT32 CCSIDR = ReadCCSIDR (0);
-
- LineSize = (1 << ((CCSIDR & 0x7) + 2));
- Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
- NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
-
- // LineSize is in words (4 byte chunks)
- return NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (0);
-
- return ((CCSIDR >> 3) & 0x3ff) + 1;
-}
-
-UINTN
-ArmDataCacheSets (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (0);
-
- return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (0) & 7;
-
- // * 4 converts to bytes
- return (1 << (CCSIDR + 2)) * 4;
-}
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
- VOID
- )
-{
- UINT32 CLIDR = ReadCLIDR ();
-
- if ((CLIDR & 1) == 1) {
- // Instruction cache exists
- return TRUE;
- }
- if ((CLIDR & 0x7) == 0x4) {
- // Unified cache
- return TRUE;
- }
-
- return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
- VOID
- )
-{
- UINT32 NumSets;
- UINT32 Associativity;
- UINT32 LineSize;
- UINT32 CCSIDR = ReadCCSIDR (1);
-
- LineSize = (1 << ((CCSIDR & 0x7) + 2));
- Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
- NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
-
- // LineSize is in words (4 byte chunks)
- return NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (1);
-
- return ((CCSIDR >> 3) & 0x3ff) + 1;
-// return 4;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSets (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (1);
-
- return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (1) & 7;
-
- // * 4 converts to bytes
- return (1 << (CCSIDR + 2)) * 4;
-
-// return 64;
-}
-
-
-VOID
-ArmV7DataCacheOperation (
- IN ARM_V7_CACHE_OPERATION DataCacheOperation
- )
-{
- UINTN SavedInterruptState;
-
- SavedInterruptState = ArmGetInterruptState ();
- ArmDisableInterrupts ();
-
- ArmV7AllDataCachesOperation (DataCacheOperation);
-
- ArmDrainWriteBuffer ();
-
- if (SavedInterruptState) {
- ArmEnableInterrupts ();
- }
-}
-
-
-VOID
-ArmV7PoUDataCacheOperation (
- IN ARM_V7_CACHE_OPERATION DataCacheOperation
- )
-{
- UINTN SavedInterruptState;
-
- SavedInterruptState = ArmGetInterruptState ();
- ArmDisableInterrupts ();
-
- ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
-
- ArmDrainWriteBuffer ();
-
- if (SavedInterruptState) {
- ArmEnableInterrupts ();
- }
-}
-
-VOID
-EFIAPI
-ArmInvalidateDataCache (
- VOID
- )
-{
- ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
- VOID
- )
-{
- ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCache (
- VOID
- )
-{
- ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCacheToPoU (
- VOID
- )
-{
- ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include <Uefi.h>\r
+#include <Chipset/ArmV7.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include "ArmV7Lib.h"\r
+#include "ArmLibPrivate.h"\r
+\r
+ARM_CACHE_TYPE\r
+EFIAPI\r
+ArmCacheType (\r
+ VOID\r
+ )\r
+{\r
+ return ARM_CACHE_TYPE_WRITE_BACK;\r
+}\r
+\r
+ARM_CACHE_ARCHITECTURE\r
+EFIAPI\r
+ArmCacheArchitecture (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CLIDR = ReadCLIDR ();\r
+\r
+ return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me\r
+}\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmDataCachePresent (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CLIDR = ReadCLIDR ();\r
+ \r
+ if ((CLIDR & 0x2) == 0x2) {\r
+ // Instruction cache exists\r
+ return TRUE;\r
+ }\r
+ if ((CLIDR & 0x7) == 0x4) {\r
+ // Unified cache\r
+ return TRUE;\r
+ }\r
+ \r
+ return FALSE;\r
+}\r
+ \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheSize (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 NumSets;\r
+ UINT32 Associativity;\r
+ UINT32 LineSize;\r
+ UINT32 CCSIDR = ReadCCSIDR (0);\r
+ \r
+ LineSize = (1 << ((CCSIDR & 0x7) + 2));\r
+ Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
+ NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;\r
+\r
+ // LineSize is in words (4 byte chunks)\r
+ return NumSets * Associativity * LineSize * 4; \r
+}\r
+ \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheAssociativity (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CCSIDR = ReadCCSIDR (0);\r
+\r
+ return ((CCSIDR >> 3) & 0x3ff) + 1;\r
+}\r
+ \r
+UINTN\r
+ArmDataCacheSets (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CCSIDR = ReadCCSIDR (0);\r
+ \r
+ return ((CCSIDR >> 13) & 0x7fff) + 1;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r
+\r
+ // * 4 converts to bytes\r
+ return (1 << (CCSIDR + 2)) * 4;\r
+}\r
+ \r
+BOOLEAN\r
+EFIAPI\r
+ArmInstructionCachePresent (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CLIDR = ReadCLIDR ();\r
+ \r
+ if ((CLIDR & 1) == 1) {\r
+ // Instruction cache exists\r
+ return TRUE;\r
+ }\r
+ if ((CLIDR & 0x7) == 0x4) {\r
+ // Unified cache\r
+ return TRUE;\r
+ }\r
+ \r
+ return FALSE;\r
+}\r
+ \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheSize (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 NumSets;\r
+ UINT32 Associativity;\r
+ UINT32 LineSize;\r
+ UINT32 CCSIDR = ReadCCSIDR (1);\r
+ \r
+ LineSize = (1 << ((CCSIDR & 0x7) + 2));\r
+ Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
+ NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;\r
+\r
+ // LineSize is in words (4 byte chunks)\r
+ return NumSets * Associativity * LineSize * 4; \r
+}\r
+ \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheAssociativity (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CCSIDR = ReadCCSIDR (1);\r
+\r
+ return ((CCSIDR >> 3) & 0x3ff) + 1;\r
+// return 4;\r
+}\r
+ \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheSets (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CCSIDR = ReadCCSIDR (1);\r
+ \r
+ return ((CCSIDR >> 13) & 0x7fff) + 1;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheLineLength (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r
+\r
+ // * 4 converts to bytes\r
+ return (1 << (CCSIDR + 2)) * 4;\r
+\r
+// return 64;\r
+}\r
+\r
+\r
+VOID\r
+ArmV7DataCacheOperation (\r
+ IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
+ )\r
+{\r
+ UINTN SavedInterruptState;\r
+\r
+ SavedInterruptState = ArmGetInterruptState ();\r
+ ArmDisableInterrupts ();\r
+ \r
+ ArmV7AllDataCachesOperation (DataCacheOperation);\r
+ \r
+ ArmDrainWriteBuffer ();\r
+ \r
+ if (SavedInterruptState) {\r
+ ArmEnableInterrupts ();\r
+ }\r
+}\r
+\r
+\r
+VOID\r
+ArmV7PoUDataCacheOperation (\r
+ IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
+ )\r
+{\r
+ UINTN SavedInterruptState;\r
+\r
+ SavedInterruptState = ArmGetInterruptState ();\r
+ ArmDisableInterrupts ();\r
+ \r
+ ArmV7PerformPoUDataCacheOperation (DataCacheOperation);\r
+ \r
+ ArmDrainWriteBuffer ();\r
+ \r
+ if (SavedInterruptState) {\r
+ ArmEnableInterrupts ();\r
+ }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCache (\r
+ VOID\r
+ )\r
+{\r
+ ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheToPoU (\r
+ VOID\r
+ )\r
+{\r
+ ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
+}\r
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