]> git.proxmox.com Git - mirror_edk2.git/blobdiff - ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
ArmPkg/Mmu: Support page size granularity in the initial MMU setting
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Mmu.c
index 9bb3c2690f06da89c63b083028bf34dcc24993ae..3ba66d62bfdc605ea04d529f7ff0c8a44d078c35 100644 (file)
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/ArmLib.h>\r
 #include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
 #include "ArmV7Lib.h"\r
 #include "ArmLibPrivate.h"\r
 \r
+VOID\r
+PopulateLevel2PageTable (\r
+  IN UINT32                         *SectionEntry,\r
+  IN UINT32                         PhysicalBase,\r
+  IN UINT32                         RemainLength,\r
+  IN ARM_MEMORY_REGION_ATTRIBUTES   Attributes\r
+  ) {\r
+  UINT32* PageEntry;\r
+  UINT32  Pages;\r
+  UINT32  Index;\r
+  UINT32  PageAttributes;\r
+  UINT32  SectionDescriptor;\r
+  UINT32  TranslationTable;\r
+  UINT32  BaseSectionAddress;\r
+\r
+  switch (Attributes) {\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:\r
+      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
+      break;\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:\r
+      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r
+      break;\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:\r
+      PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;\r
+      break;\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:\r
+      PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
+      break;\r
+    default:\r
+      PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
+      break;\r
+  }\r
+\r
+  // Check if the Section Entry has already been populated. Otherwise attach a\r
+  // Level 2 Translation Table to it\r
+  if (*SectionEntry != 0) {\r
+    // The entry must be a page table. Otherwise it exists an overlapping in the memory map\r
+    if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {\r
+      TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;\r
+    } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
+      // Case where a virtual memory map descriptor overlapped a section entry\r
+\r
+      // Allocate a Level2 Page Table for this Section\r
+      TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r
+      TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r
+\r
+      // Translate the Section Descriptor into Page Descriptor\r
+      SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
+      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*SectionEntry,0);\r
+      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*SectionEntry);\r
+      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(*SectionEntry,0);\r
+      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(*SectionEntry);\r
+      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(*SectionEntry);\r
+\r
+      BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);\r
+\r
+      // Populate the new Level2 Page Table for the section\r
+      PageEntry = (UINT32*)TranslationTable;\r
+      for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
+        PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r
+      }\r
+\r
+      // Overwrite the section entry to point to the new Level2 Translation Table\r
+      *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
+          (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
+          TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
+    } else {\r
+      // We do not support the other section type (16MB Section)\r
+      ASSERT(0);\r
+      return;\r
+    }\r
+  } else {\r
+    TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r
+    TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r
+\r
+    ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);\r
+\r
+    *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
+        (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
+        TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
+  }\r
+\r
+  PageEntry = ((UINT32 *)(TranslationTable) + ((PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
+  Pages     = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
+\r
+  for (Index = 0; Index < Pages; Index++) {\r
+    *PageEntry++     =  TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;\r
+    PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;\r
+  }\r
+\r
+}\r
+\r
 VOID\r
 FillTranslationTable (\r
   IN  UINT32                        *TranslationTable,\r
   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion\r
   )\r
 {\r
-  UINT32  *Entry;\r
-  UINTN   Sections;\r
-  UINTN   Index;\r
+  UINT32  *SectionEntry;\r
   UINT32  Attributes;\r
   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;\r
+  UINT32  RemainLength = MemoryRegion->Length;\r
   \r
+  ASSERT(MemoryRegion->Length > 0);\r
+\r
   switch (MemoryRegion->Attributes) {\r
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
@@ -64,12 +162,34 @@ FillTranslationTable (
       break;\r
   }\r
   \r
-  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
-  Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;\r
-  \r
-  for (Index = 0; Index < Sections; Index++) {\r
-    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
-    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
+  // Get the first section entry for this mapping\r
+  SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
+\r
+  while (RemainLength != 0) {\r
+    if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) {\r
+      if (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r
+        // Case: Physical address aligned on the Section Size (1MB) && the length is greater than the Section Size\r
+        *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
+        PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
+      } else {\r
+        // Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section\r
+        PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);\r
+\r
+        // It must be the last entry\r
+        break;\r
+      }\r
+    } else {\r
+      // Case: Physical address NOT aligned on the Section Size (1MB)\r
+      PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);\r
+      // Aligned the address\r
+      PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);\r
+\r
+      // If it is the last entry\r
+      if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {\r
+        break;\r
+      }\r
+    }\r
+    RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
   }\r
 }\r
 \r
@@ -111,7 +231,7 @@ ArmConfigureMmu (
   ArmCleanInvalidateDataCache();\r
   ArmInvalidateInstructionCache();\r
 \r
-  TranslationTableAttribute = 0;\r
+  TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
   while (MemoryTable->Length != 0) {\r
     // Find the memory attribute for the Translation Table\r
     if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable < MemoryTable->PhysicalBase + MemoryTable->Length)) {\r