/** @file\r
* File managing the MMU for ARMv7 architecture\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
IN UINT32 PhysicalBase,\r
IN UINT32 RemainLength,\r
IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r
- ) {\r
+ )\r
+{\r
UINT32* PageEntry;\r
UINT32 Pages;\r
UINT32 Index;\r
\r
switch (Attributes) {\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
break;\r
default:\r
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);\r
break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
break;\r
default:\r
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
} else {\r
// Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section\r
- PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);\r
+ PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r
\r
// It must be the last entry\r
break;\r
}\r
} else {\r
// Case: Physical address NOT aligned on the Section Size (1MB)\r
- PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);\r
+ PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r
// Aligned the address\r
PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);\r
\r
UINT32 TTBRAttributes;\r
\r
// Allocate pages for translation table.\r
- TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));\r
+ TranslationTable = (UINTN)AllocatePages (EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));\r
TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK;\r
\r
if (TranslationTableBase != NULL) {\r
*TranslationTableBase = (VOID *)TranslationTable;\r
}\r
\r
- if (TranslationTableBase != NULL) {\r
+ if (TranslationTableSize != NULL) {\r
*TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;\r
}\r
\r
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r
\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
- ArmInvalidateTlb();\r
+ ArmCleanInvalidateDataCache ();\r
+ ArmInvalidateInstructionCache ();\r
+ ArmInvalidateTlb ();\r
\r
- ArmDisableDataCache();\r
+ ArmDisableDataCache ();\r
ArmDisableInstructionCache();\r
- ArmDisableMmu();\r
+ ArmDisableMmu ();\r
\r
// Make sure nothing sneaked into the cache\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
+ ArmCleanInvalidateDataCache ();\r
+ ArmInvalidateInstructionCache ();\r
\r
TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
while (MemoryTable->Length != 0) {\r
// Find the memory attribute for the Translation Table\r
- if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable < MemoryTable->PhysicalBase + MemoryTable->Length)) {\r
+ if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r
TranslationTableAttribute = MemoryTable->Attributes;\r
}\r
\r
\r
// Translate the Memory Attributes into Translation Table Register Attributes\r
if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || \r
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED)) {\r
+ (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r
TTBRAttributes = TTBR_NON_CACHEABLE;\r
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || \r
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK)) {\r
+ (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
TTBRAttributes = TTBR_WRITE_BACK_ALLOC;\r
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || \r
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH)) {\r
+ (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r
TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;\r
} else {\r
//TODO: We should raise an error here\r
TTBRAttributes = TTBR_NON_CACHEABLE;\r
}\r
\r
- ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & 0xFFFFC000) | (TTBRAttributes & 0x7F)));\r
+ ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));\r
\r
ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r
DOMAIN_ACCESS_CONTROL_NONE(14) |\r