-Loop4:\r
- add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r
- mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r
- and R12, R12, #7 @ get those 3 bits alone\r
- cmp R12, #2\r
- blt Skip2 @ no cache or only instruction cache at this level\r
- mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb @ isb to sync the change to the CacheSizeID reg \r
- mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r
- and R2, R12, #0x7 @ extract the line length field\r
- add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r
- ldr R4, =0x3FF\r
- ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r
- clz R5, R4 @ R5 is the bit position of the way size increment\r
- ldr R7, =0x00007FFF\r
- ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r
-\r
-Loop5:\r
- mov R9, R4 @ R9 working copy of the max way size (right aligned)\r
-\r
-Loop6:\r
- orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r
- orr R0, R0, R7, LSL R2 @ factor in the index number\r
-\r
- blx R1\r
-\r
- subs R9, R9, #1 @ decrement the way number\r
- bge Loop6\r
- subs R7, R7, #1 @ decrement the index\r
- bge Loop5\r
-Skip2:\r
- add R10, R10, #2 @ increment the cache number\r
- cmp R3, R10\r
- bgt Loop4\r
- \r
-Finished2:\r