ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLib

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.S

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index f59cd5f32e6b2ef2d51f4be5e0f1da981f56035a..47a4aa5e0d4e0d27714df602cdb5bba46f98c9e9 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -18,12 +18,13 @@
 \r
 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r
 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmDrainWriteBuffer)\r
 GCC_ASM_EXPORT (ArmEnableMmu)\r
 GCC_ASM_EXPORT (ArmDisableMmu)\r
 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r
@@ -38,7 +39,6 @@ GCC_ASM_EXPORT (ArmDisableBranchPrediction)
 GCC_ASM_EXPORT (ArmSetLowVectors)\r
 GCC_ASM_EXPORT (ArmSetHighVectors)\r
 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)\r
-GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)\r
 GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
@@ -63,42 +63,39 @@ GCC_ASM_EXPORT (ArmReadIdPfr1)
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
+ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r
+  mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU\r
+  bx      lr\r
+\r
+ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):\r
+  mcr     p15, 0, r0, c7, c5, 1  @Invalidate single instruction cache line to PoU\r
+  mcr     p15, 0, r0, c7, c5, 7  @Invalidate branch predictor\r
+  bx      lr\r
+\r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmInvalidateInstructionCache):\r
@@ -268,61 +265,11 @@ L_Finished:
   ldmfd SP!, {r4-r12, lr}\r
   bx    LR\r
 \r
-ASM_PFX(ArmV7PerformPoUDataCacheOperation):\r
-  stmfd SP!,{r4-r12, LR}\r
-  mov   R1, R0                @ Save Function call in R1\r
-  mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
-  ands  R3, R6, #0x38000000    @ Mask out all but Level of Unification (LoU)\r
-  mov   R3, R3, LSR #26       @ Cache level value (naturally aligned)\r
-  beq   Finished2\r
-  mov   R10, #0\r
-\r
-Loop4:\r
-  add   R2, R10, R10, LSR #1    @ Work out 3xcachelevel\r
-  mov   R12, R6, LSR R2         @ bottom 3 bits are the Cache type for this level\r
-  and   R12, R12, #7            @ get those 3 bits alone\r
-  cmp   R12, #2\r
-  blt   Skip2                   @ no cache or only instruction cache at this level\r
-  mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
-  isb                           @ isb to sync the change to the CacheSizeID reg\r
-  mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)\r
-  and   R2, R12, #0x7            @ extract the line length field\r
-  add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)\r
-  ldr   R4, =0x3FF\r
-  ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)\r
-  clz   R5, R4                  @ R5 is the bit position of the way size increment\r
-  ldr   R7, =0x00007FFF\r
-  ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)\r
-\r
-Loop5:\r
-  mov   R9, R4                  @ R9 working copy of the max way size (right aligned)\r
-\r
-Loop6:\r
-  orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11\r
-  orr   R0, R0, R7, LSL R2      @ factor in the index number\r
-\r
-  blx   R1\r
-\r
-  subs  R9, R9, #1              @ decrement the way number\r
-  bge   Loop6\r
-  subs  R7, R7, #1              @ decrement the index\r
-  bge   Loop5\r
-Skip2:\r
-  add   R10, R10, #2            @ increment the cache number\r
-  cmp   R3, R10\r
-  bgt   Loop4\r
-\r
-Finished2:\r
-  dsb\r
-  ldmfd SP!, {r4-r12, lr}\r
-  bx    LR\r
-\r
 ASM_PFX(ArmDataMemoryBarrier):\r
   dmb\r
   bx      LR\r
 \r
 ASM_PFX(ArmDataSynchronizationBarrier):\r
-ASM_PFX(ArmDrainWriteBuffer):\r
   dsb\r
   bx      LR\r
 \r
@@ -355,7 +302,11 @@ ASM_PFX(ArmEnableVFP):
   isb\r
   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
   mov     r0, #0x40000000\r
+#ifndef __clang__\r
   mcr     p10,#0x7,r0,c8,c0,#0\r
+#else\r
+  vmsr    fpexc, r0\r
+#endif\r
   bx      lr\r
 \r
 ASM_PFX(ArmCallWFI):\r