ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLib

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.S

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index fdc4d03776c8af17f74532b4e1331d5fd59588dc..47a4aa5e0d4e0d27714df602cdb5bba46f98c9e9 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -18,12 +18,13 @@
 \r
 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r
 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmDrainWriteBuffer)\r
 GCC_ASM_EXPORT (ArmEnableMmu)\r
 GCC_ASM_EXPORT (ArmDisableMmu)\r
 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r
@@ -62,42 +63,39 @@ GCC_ASM_EXPORT (ArmReadIdPfr1)
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
+ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r
+  mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU\r
+  bx      lr\r
+\r
+ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):\r
+  mcr     p15, 0, r0, c7, c5, 1  @Invalidate single instruction cache line to PoU\r
+  mcr     p15, 0, r0, c7, c5, 7  @Invalidate branch predictor\r
+  bx      lr\r
+\r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmInvalidateInstructionCache):\r
@@ -272,7 +270,6 @@ ASM_PFX(ArmDataMemoryBarrier):
   bx      LR\r
 \r
 ASM_PFX(ArmDataSynchronizationBarrier):\r
-ASM_PFX(ArmDrainWriteBuffer):\r
   dsb\r
   bx      LR\r
 \r
@@ -305,7 +302,11 @@ ASM_PFX(ArmEnableVFP):
   isb\r
   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
   mov     r0, #0x40000000\r
+#ifndef __clang__\r
   mcr     p10,#0x7,r0,c8,c0,#0\r
+#else\r
+  vmsr    fpexc, r0\r
+#endif\r
   bx      lr\r
 \r
 ASM_PFX(ArmCallWFI):\r