bx lr\r
\r
\r
+ RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA\r
+ mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU\r
+ mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor\r
+ bx lr\r
+\r
+\r
RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r
mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU\r
bx lr\r