//\r
//------------------------------------------------------------------------------\r
\r
- EXPORT ArmInvalidateInstructionCache\r
- EXPORT ArmInvalidateDataCacheEntryByMVA\r
- EXPORT ArmCleanDataCacheEntryByMVA\r
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
- EXPORT ArmInvalidateDataCacheEntryBySetWay\r
- EXPORT ArmCleanDataCacheEntryBySetWay\r
- EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
- EXPORT ArmDrainWriteBuffer\r
- EXPORT ArmEnableMmu\r
- EXPORT ArmDisableMmu\r
- EXPORT ArmDisableCachesAndMmu\r
- EXPORT ArmMmuEnabled\r
- EXPORT ArmEnableDataCache\r
- EXPORT ArmDisableDataCache\r
- EXPORT ArmEnableInstructionCache\r
- EXPORT ArmDisableInstructionCache\r
- EXPORT ArmEnableSWPInstruction\r
- EXPORT ArmEnableBranchPrediction\r
- EXPORT ArmDisableBranchPrediction\r
- EXPORT ArmSetLowVectors\r
- EXPORT ArmSetHighVectors\r
- EXPORT ArmV7AllDataCachesOperation\r
- EXPORT ArmDataMemoryBarrier\r
- EXPORT ArmDataSynchronizationBarrier\r
- EXPORT ArmInstructionSynchronizationBarrier\r
- EXPORT ArmReadVBar\r
- EXPORT ArmWriteVBar\r
- EXPORT ArmEnableVFP\r
- EXPORT ArmCallWFI\r
- EXPORT ArmReadCbar\r
- EXPORT ArmReadMpidr\r
- EXPORT ArmReadTpidrurw\r
- EXPORT ArmWriteTpidrurw\r
- EXPORT ArmIsArchTimerImplemented\r
- EXPORT ArmReadIdPfr1\r
-\r
- AREA ArmV7Support, CODE, READONLY\r
+\r
+ INCLUDE AsmMacroExport.inc\r
PRESERVE8\r
\r
DC_ON EQU ( 0x1:SHL:2 )\r
CTRL_I_BIT EQU (1 << 12)\r
\r
\r
-ArmInvalidateDataCacheEntryByMVA\r
+ RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
- dsb\r
- isb\r
bx lr\r
\r
-ArmCleanDataCacheEntryByMVA\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
- dsb\r
- isb\r
bx lr\r
\r
\r
-ArmCleanInvalidateDataCacheEntryByMVA\r
+ RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA\r
+ mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU\r
+ mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r
+ mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
- dsb\r
- isb\r
bx lr\r
\r
\r
-ArmInvalidateDataCacheEntryBySetWay\r
+ RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
- dsb\r
- isb\r
bx lr\r
\r
\r
-ArmCleanInvalidateDataCacheEntryBySetWay\r
+ RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
- dsb\r
- isb\r
bx lr\r
\r
\r
-ArmCleanDataCacheEntryBySetWay\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r
mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
- dsb\r
- isb\r
bx lr\r
\r
\r
-ArmInvalidateInstructionCache\r
+ RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r
mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
isb\r
bx LR\r
\r
-ArmEnableMmu\r
+ RVCT_ASM_EXPORT ArmEnableMmu\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmDisableMmu\r
+ RVCT_ASM_EXPORT ArmDisableMmu\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmDisableCachesAndMmu\r
+ RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r
mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
isb\r
bx LR\r
\r
-ArmMmuEnabled\r
+ RVCT_ASM_EXPORT ArmMmuEnabled\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
and R0,R0,#1\r
bx LR\r
\r
-ArmEnableDataCache\r
+ RVCT_ASM_EXPORT ArmEnableDataCache\r
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
isb\r
bx LR\r
\r
-ArmDisableDataCache\r
+ RVCT_ASM_EXPORT ArmDisableDataCache\r
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
isb\r
bx LR\r
\r
-ArmEnableInstructionCache\r
+ RVCT_ASM_EXPORT ArmEnableInstructionCache\r
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
isb\r
bx LR\r
\r
-ArmDisableInstructionCache\r
+ RVCT_ASM_EXPORT ArmDisableInstructionCache\r
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
isb\r
bx LR\r
\r
-ArmEnableSWPInstruction\r
+ RVCT_ASM_EXPORT ArmEnableSWPInstruction\r
mrc p15, 0, r0, c1, c0, 0\r
orr r0, r0, #0x00000400\r
mcr p15, 0, r0, c1, c0, 0\r
isb\r
bx LR\r
\r
-ArmEnableBranchPrediction\r
+ RVCT_ASM_EXPORT ArmEnableBranchPrediction\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr r0, r0, #0x00000800 ;\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmDisableBranchPrediction\r
+ RVCT_ASM_EXPORT ArmDisableBranchPrediction\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic r0, r0, #0x00000800 ;\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmSetLowVectors\r
+ RVCT_ASM_EXPORT ArmSetLowVectors\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic r0, r0, #0x00002000 ; clear V bit\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmSetHighVectors\r
+ RVCT_ASM_EXPORT ArmSetHighVectors\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr r0, r0, #0x00002000 ; Set V bit\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmV7AllDataCachesOperation\r
+ RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r
stmfd SP!,{r4-r12, LR}\r
mov R1, R0 ; Save Function call in R1\r
mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
ldmfd SP!, {r4-r12, lr}\r
bx LR\r
\r
-ArmDataMemoryBarrier\r
+ RVCT_ASM_EXPORT ArmDataMemoryBarrier\r
dmb\r
bx LR\r
\r
-ArmDataSynchronizationBarrier\r
-ArmDrainWriteBuffer\r
+ RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r
dsb\r
bx LR\r
\r
-ArmInstructionSynchronizationBarrier\r
+ RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r
isb\r
bx LR\r
\r
-ArmReadVBar\r
+ RVCT_ASM_EXPORT ArmReadVBar\r
// Set the Address of the Vector Table in the VBAR register\r
mrc p15, 0, r0, c12, c0, 0\r
bx lr\r
\r
-ArmWriteVBar\r
+ RVCT_ASM_EXPORT ArmWriteVBar\r
// Set the Address of the Vector Table in the VBAR register\r
mcr p15, 0, r0, c12, c0, 0\r
// Ensure the SCTLR.V bit is clear\r
isb\r
bx lr\r
\r
-ArmEnableVFP\r
+ RVCT_ASM_EXPORT ArmEnableVFP\r
// Read CPACR (Coprocessor Access Control Register)\r
mrc p15, 0, r0, c1, c0, 2\r
// Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
mcr p10,#0x7,r0,c8,c0,#0\r
bx lr\r
\r
-ArmCallWFI\r
+ RVCT_ASM_EXPORT ArmCallWFI\r
wfi\r
bx lr\r
\r
//Note: Return 0 in Uniprocessor implementation\r
-ArmReadCbar\r
+ RVCT_ASM_EXPORT ArmReadCbar\r
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
bx lr\r
\r
-ArmReadMpidr\r
+ RVCT_ASM_EXPORT ArmReadMpidr\r
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
bx lr\r
\r
-ArmReadTpidrurw\r
+ RVCT_ASM_EXPORT ArmReadTpidrurw\r
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
bx lr\r
\r
-ArmWriteTpidrurw\r
+ RVCT_ASM_EXPORT ArmWriteTpidrurw\r
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
bx lr\r
\r
-ArmIsArchTimerImplemented\r
+ RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
and r0, r0, #0x000F0000\r
bx lr\r
\r
-ArmReadIdPfr1\r
+ RVCT_ASM_EXPORT ArmReadIdPfr1\r
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
bx lr\r
\r
projects / mirror_edk2.git / blobdiff