-//------------------------------------------------------------------------------ \r
+//------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
EXPORT ArmInvalidateDataCacheEntryBySetWay\r
EXPORT ArmCleanDataCacheEntryBySetWay\r
EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
- EXPORT ArmDrainWriteBuffer\r
EXPORT ArmEnableMmu\r
EXPORT ArmDisableMmu\r
EXPORT ArmDisableCachesAndMmu\r
EXPORT ArmSetLowVectors\r
EXPORT ArmSetHighVectors\r
EXPORT ArmV7AllDataCachesOperation\r
- EXPORT ArmV7PerformPoUDataCacheOperation\r
EXPORT ArmDataMemoryBarrier\r
- EXPORT ArmDataSyncronizationBarrier\r
+ EXPORT ArmDataSynchronizationBarrier\r
EXPORT ArmInstructionSynchronizationBarrier\r
EXPORT ArmReadVBar\r
EXPORT ArmWriteVBar\r
EXPORT ArmEnableVFP\r
EXPORT ArmCallWFI\r
EXPORT ArmReadCbar\r
- EXPORT ArmInvalidateInstructionAndDataTlb\r
EXPORT ArmReadMpidr\r
EXPORT ArmReadTpidrurw\r
EXPORT ArmWriteTpidrurw\r
EXPORT ArmIsArchTimerImplemented\r
EXPORT ArmReadIdPfr1\r
+ EXPORT ArmReadIdMmfr0\r
\r
AREA ArmV7Support, CODE, READONLY\r
PRESERVE8\r
\r
\r
ArmInvalidateDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line \r
- dsb\r
- isb\r
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
bx lr\r
\r
ArmCleanDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line \r
- dsb\r
- isb\r
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
bx lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryByMVA\r
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
- dsb\r
- isb\r
bx lr\r
\r
\r
ArmInvalidateDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line \r
- dsb\r
- isb\r
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
bx lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line \r
- dsb\r
- isb\r
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
bx lr\r
\r
\r
ArmCleanDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line \r
- dsb\r
- isb\r
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
bx lr\r
\r
\r
dsb\r
isb\r
bx LR\r
- \r
+\r
ArmDisableDataCache\r
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
dsb\r
isb\r
bx LR\r
- \r
+\r
ArmDisableInstructionCache\r
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
\r
ArmSetHighVectors\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00002000 ; clear V bit\r
+ orr r0, r0, #0x00002000 ; Set V bit\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
beq Finished\r
mov R10, #0\r
\r
-Loop1 \r
+Loop1\r
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
and R12, R12, #7 ; get those 3 bits alone\r
cmp R12, #2\r
blt Skip ; no cache or only instruction cache at this level\r
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb ; isb to sync the change to the CacheSizeID reg \r
+ isb ; isb to sync the change to the CacheSizeID reg\r
mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
and R2, R12, #&7 ; extract the line length field\r
add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
ldr R7, =0x00007FFF\r
ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
\r
-Loop2 \r
+Loop2\r
mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
\r
-Loop3 \r
+Loop3\r
orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
orr R0, R0, R7, LSL R2 ; factor in the index number\r
\r
bge Loop3\r
subs R7, R7, #1 ; decrement the index\r
bge Loop2\r
-Skip \r
+Skip\r
add R10, R10, #2 ; increment the cache number\r
cmp R3, R10\r
bgt Loop1\r
- \r
-Finished\r
- dsb\r
- ldmfd SP!, {r4-r12, lr}\r
- bx LR\r
-\r
-ArmV7PerformPoUDataCacheOperation\r
- stmfd SP!,{r4-r12, LR}\r
- mov R1, R0 ; Save Function call in R1\r
- mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
- ands R3, R6, #&38000000 ; Mask out all but Level of Unification (LoU)\r
- mov R3, R3, LSR #26 ; Cache level value (naturally aligned)\r
- beq Finished2\r
- mov R10, #0\r
-\r
-Loop4 \r
- add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
- mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
- and R12, R12, #7 ; get those 3 bits alone\r
- cmp R12, #2\r
- blt Skip2 ; no cache or only instruction cache at this level\r
- mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb ; isb to sync the change to the CacheSizeID reg \r
- mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
- and R2, R12, #&7 ; extract the line length field\r
- add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
- ldr R4, =0x3FF\r
- ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
- clz R5, R4 ; R5 is the bit position of the way size increment\r
- ldr R7, =0x00007FFF\r
- ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
-\r
-Loop5 \r
- mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
-\r
-Loop6 \r
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
- orr R0, R0, R7, LSL R2 ; factor in the index number\r
-\r
- blx R1\r
\r
- subs R9, R9, #1 ; decrement the way number\r
- bge Loop6\r
- subs R7, R7, #1 ; decrement the index\r
- bge Loop5\r
-Skip2 \r
- add R10, R10, #2 ; increment the cache number\r
- cmp R3, R10\r
- bgt Loop4\r
- \r
-Finished2\r
+Finished\r
dsb\r
ldmfd SP!, {r4-r12, lr}\r
bx LR\r
ArmDataMemoryBarrier\r
dmb\r
bx LR\r
- \r
-ArmDataSyncronizationBarrier\r
-ArmDrainWriteBuffer\r
+\r
+ArmDataSynchronizationBarrier\r
dsb\r
bx LR\r
- \r
+\r
ArmInstructionSynchronizationBarrier\r
isb\r
bx LR\r
\r
ArmWriteVBar\r
// Set the Address of the Vector Table in the VBAR register\r
- mcr p15, 0, r0, c12, c0, 0 \r
+ mcr p15, 0, r0, c12, c0, 0\r
// Ensure the SCTLR.V bit is clear\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic r0, r0, #0x00002000 ; clear V bit\r
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
bx lr\r
\r
-ArmInvalidateInstructionAndDataTlb\r
- mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB\r
- dsb\r
- bx lr\r
-\r
ArmReadMpidr\r
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
bx lr\r
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
bx lr\r
\r
+ArmReadIdMmfr0\r
+ mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register\r
+ bx lr\r
+\r
END\r
projects / mirror_edk2.git / blobdiff