- ADD R2, R10, R10, LSR #1 ; Work out 3xcachelevel
- MOV R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
- AND R12, R12, #7 ; get those 3 bits alone
- CMP R12, #2
- BLT Skip ; no cache or only instruction cache at this level
- MCR p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
- ISB ; ISB to sync the change to the CacheSizeID reg
- MRC p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
- AND R2, R12, #&7 ; extract the line length field
- ADD R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
- LDR R4, =0x3FF
- ANDS R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
- CLZ R5, R4 ; R5 is the bit position of the way size increment
- LDR R7, =0x00007FFF
- ANDS R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
+ add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
+ mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
+ and R12, R12, #7 ; get those 3 bits alone
+ cmp R12, #2
+ blt Skip ; no cache or only instruction cache at this level
+ mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
+ isb ; isb to sync the change to the CacheSizeID reg
+ mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
+ and R2, R12, #&7 ; extract the line length field
+ add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
+ ldr R4, =0x3FF
+ ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
+ clz R5, R4 ; R5 is the bit position of the way size increment
+ ldr R7, =0x00007FFF
+ ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)