-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
- EXPORT ArmInvalidateInstructionCache
- EXPORT ArmInvalidateDataCacheEntryByMVA
- EXPORT ArmCleanDataCacheEntryByMVA
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA
- EXPORT ArmInvalidateDataCacheEntryBySetWay
- EXPORT ArmCleanDataCacheEntryBySetWay
- EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
- EXPORT ArmDrainWriteBuffer
- EXPORT ArmEnableMmu
- EXPORT ArmDisableMmu
- EXPORT ArmDisableCachesAndMmu
- EXPORT ArmMmuEnabled
- EXPORT ArmEnableDataCache
- EXPORT ArmDisableDataCache
- EXPORT ArmEnableInstructionCache
- EXPORT ArmDisableInstructionCache
- EXPORT ArmEnableSWPInstruction
- EXPORT ArmEnableBranchPrediction
- EXPORT ArmDisableBranchPrediction
- EXPORT ArmSetLowVectors
- EXPORT ArmSetHighVectors
- EXPORT ArmV7AllDataCachesOperation
- EXPORT ArmDataMemoryBarrier
- EXPORT ArmDataSyncronizationBarrier
- EXPORT ArmInstructionSynchronizationBarrier
- EXPORT ArmWriteNsacr
- EXPORT ArmWriteScr
- EXPORT ArmWriteVMBar
- EXPORT ArmWriteVBar
- EXPORT ArmReadVBar
- EXPORT ArmWriteCPACR
- EXPORT ArmEnableVFP
- EXPORT ArmCallWFI
- EXPORT ArmWriteAuxCr
- EXPORT ArmReadAuxCr
- EXPORT ArmReadCbar
- EXPORT ArmInvalidateInstructionAndDataTlb
- EXPORT ArmReadMpidr
- EXPORT ArmReadTpidrurw
- EXPORT ArmWriteTpidrurw
-
- AREA ArmCacheLib, CODE, READONLY
- PRESERVE8
-
-DC_ON EQU ( 0x1:SHL:2 )
-IC_ON EQU ( 0x1:SHL:12 )
-CTRL_M_BIT EQU (1 << 0)
-CTRL_C_BIT EQU (1 << 2)
-CTRL_B_BIT EQU (1 << 7)
-CTRL_I_BIT EQU (1 << 12)
-
-
-ArmInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
- dsb
- isb
- bx lr
-
-
-ArmCleanDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
- dsb
- isb
- bx lr
-
-
-ArmCleanInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
- dsb
- isb
- bx lr
-
-
-ArmInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
- dsb
- isb
- bx lr
-
-
-ArmCleanInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
- dsb
- isb
- bx lr
-
-
-ArmCleanDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line
- dsb
- isb
- bx lr
-
-
-ArmInvalidateInstructionCache
- mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
- isb
- bx LR
-
-ArmEnableMmu
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- dsb
- isb
- bx LR
-
-ArmMmuEnabled
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- and R0,R0,#1
- bx LR
-
-ArmDisableMmu
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
-
- mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
- mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
- dsb
- isb
- bx LR
-
-ArmDisableCachesAndMmu
- mrc p15, 0, r0, c1, c0, 0 ; Get control register
- bic r0, r0, #CTRL_M_BIT ; Disable MMU
- bic r0, r0, #CTRL_C_BIT ; Disable D Cache
- bic r0, r0, #CTRL_I_BIT ; Disable I Cache
- mcr p15, 0, r0, c1, c0, 0 ; Write control register
- dsb
- isb
- bx LR
-
-ArmEnableDataCache
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- dsb
- isb
- bx LR
-
-ArmDisableDataCache
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmEnableInstructionCache
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- dsb
- isb
- bx LR
-
-ArmDisableInstructionCache
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmEnableSWPInstruction
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000400
- mcr p15, 0, r0, c1, c0, 0
- isb
- bx LR
-
-ArmEnableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00000800 ;
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmDisableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00000800 ;
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmSetLowVectors
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00002000 ; clear V bit
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmSetHighVectors
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00002000 ; clear V bit
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmV7AllDataCachesOperation
- stmfd SP!,{r4-r12, LR}
- mov R1, R0 ; Save Function call in R1
- mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
- ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
- mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
- beq Finished
- mov R10, #0
-
-Loop1
- add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
- mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
- and R12, R12, #7 ; get those 3 bits alone
- cmp R12, #2
- blt Skip ; no cache or only instruction cache at this level
- mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
- isb ; isb to sync the change to the CacheSizeID reg
- mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
- and R2, R12, #&7 ; extract the line length field
- add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
- ldr R4, =0x3FF
- ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
- clz R5, R4 ; R5 is the bit position of the way size increment
- ldr R7, =0x00007FFF
- ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
-
-Loop2
- mov R9, R4 ; R9 working copy of the max way size (right aligned)
-
-Loop3
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
- orr R0, R0, R7, LSL R2 ; factor in the index number
-
- blx R1
-
- subs R9, R9, #1 ; decrement the way number
- bge Loop3
- subs R7, R7, #1 ; decrement the index
- bge Loop2
-Skip
- add R10, R10, #2 ; increment the cache number
- cmp R3, R10
- bgt Loop1
-
-Finished
- dsb
- ldmfd SP!, {r4-r12, lr}
- bx LR
-
-
-ArmDataMemoryBarrier
- dmb
- bx LR
-
-ArmDataSyncronizationBarrier
-ArmDrainWriteBuffer
- dsb
- bx LR
-
-ArmInstructionSynchronizationBarrier
- isb
- bx LR
-
-ArmWriteNsacr
- mcr p15, 0, r0, c1, c1, 2
- bx lr
-
-ArmWriteScr
- mcr p15, 0, r0, c1, c1, 0
- bx lr
-
-ArmWriteAuxCr
- mcr p15, 0, r0, c1, c0, 1
- bx lr
-
-ArmReadAuxCr
- mrc p15, 0, r0, c1, c0, 1
- bx lr
-
-ArmWriteVMBar
- mcr p15, 0, r0, c12, c0, 1
- bx lr
-
-ArmWriteVBar
- // Set the Address of the Vector Table in the VBAR register
- mcr p15, 0, r0, c12, c0, 0
- // Ensure the SCTLR.V bit is clear
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00002000 ; clear V bit
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx lr
-
-ArmReadVBar
- mrc p15, 0, r0, c12, c0, 0
- bx lr
-
-ArmWriteCPACR
- mcr p15, 0, r0, c1, c0, 2
- bx lr
-
-ArmEnableVFP
- // Read CPACR (Coprocessor Access Control Register)
- mrc p15, 0, r0, c1, c0, 2
- // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
- orr r0, r0, #0x00f00000
- // Write back CPACR (Coprocessor Access Control Register)
- mcr p15, 0, r0, c1, c0, 2
- // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
- mov r0, #0x40000000
- mcr p10,#0x7,r0,c8,c0,#0
- bx lr
-
-ArmCallWFI
- wfi
- bx lr
-
-//Note: Return 0 in Uniprocessor implementation
-ArmReadCbar
- mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
- bx lr
-
-ArmInvalidateInstructionAndDataTlb
- mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
- dsb
- bx lr
-
-ArmReadMpidr
- mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
- bx lr
-
-ArmReadTpidrurw
- mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
- bx lr
-
-ArmWriteTpidrurw
- mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
- bx lr
-
- END
-
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ EXPORT ArmInvalidateInstructionCache\r
+ EXPORT ArmInvalidateDataCacheEntryByMVA\r
+ EXPORT ArmCleanDataCacheEntryByMVA\r
+ EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
+ EXPORT ArmInvalidateDataCacheEntryBySetWay\r
+ EXPORT ArmCleanDataCacheEntryBySetWay\r
+ EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
+ EXPORT ArmDrainWriteBuffer\r
+ EXPORT ArmEnableMmu\r
+ EXPORT ArmDisableMmu\r
+ EXPORT ArmDisableCachesAndMmu\r
+ EXPORT ArmMmuEnabled\r
+ EXPORT ArmEnableDataCache\r
+ EXPORT ArmDisableDataCache\r
+ EXPORT ArmEnableInstructionCache\r
+ EXPORT ArmDisableInstructionCache\r
+ EXPORT ArmEnableSWPInstruction\r
+ EXPORT ArmEnableBranchPrediction\r
+ EXPORT ArmDisableBranchPrediction\r
+ EXPORT ArmSetLowVectors\r
+ EXPORT ArmSetHighVectors\r
+ EXPORT ArmV7AllDataCachesOperation\r
+ EXPORT ArmDataMemoryBarrier\r
+ EXPORT ArmDataSyncronizationBarrier\r
+ EXPORT ArmInstructionSynchronizationBarrier\r
+ EXPORT ArmWriteVBar\r
+ EXPORT ArmEnableVFP\r
+ EXPORT ArmCallWFI\r
+ EXPORT ArmReadCbar\r
+ EXPORT ArmInvalidateInstructionAndDataTlb\r
+ EXPORT ArmReadMpidr\r
+ EXPORT ArmReadTpidrurw\r
+ EXPORT ArmWriteTpidrurw\r
+ EXPORT ArmIsArchTimerImplemented\r
+ EXPORT ArmReadIdPfr1\r
+\r
+ AREA ArmV7Support, CODE, READONLY\r
+ PRESERVE8\r
+\r
+DC_ON EQU ( 0x1:SHL:2 )\r
+IC_ON EQU ( 0x1:SHL:12 )\r
+CTRL_M_BIT EQU (1 << 0)\r
+CTRL_C_BIT EQU (1 << 2)\r
+CTRL_B_BIT EQU (1 << 7)\r
+CTRL_I_BIT EQU (1 << 12)\r
+\r
+\r
+ArmInvalidateDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ArmCleanDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmCleanInvalidateDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmInvalidateDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmCleanInvalidateDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmCleanDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmInvalidateInstructionCache\r
+ mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableMmu\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableMmu\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+\r
+ mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
+ mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableCachesAndMmu\r
+ mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
+ bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
+ bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
+ bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmMmuEnabled\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ and R0,R0,#1\r
+ bx LR\r
+\r
+ArmEnableDataCache\r
+ ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+ \r
+ArmDisableDataCache\r
+ ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableInstructionCache\r
+ ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+ \r
+ArmDisableInstructionCache\r
+ ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableSWPInstruction\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ orr r0, r0, #0x00000400\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableBranchPrediction\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00000800 ;\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableBranchPrediction\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00000800 ;\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmSetLowVectors\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ArmSetHighVectors\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ArmV7AllDataCachesOperation\r
+ stmfd SP!,{r4-r12, LR}\r
+ mov R1, R0 ; Save Function call in R1\r
+ mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
+ ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
+ mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
+ beq Finished\r
+ mov R10, #0\r
+\r
+Loop1 \r
+ add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
+ mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
+ and R12, R12, #7 ; get those 3 bits alone\r
+ cmp R12, #2\r
+ blt Skip ; no cache or only instruction cache at this level\r
+ mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
+ isb ; isb to sync the change to the CacheSizeID reg \r
+ mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
+ and R2, R12, #&7 ; extract the line length field\r
+ add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
+ ldr R4, =0x3FF\r
+ ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
+ clz R5, R4 ; R5 is the bit position of the way size increment\r
+ ldr R7, =0x00007FFF\r
+ ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
+\r
+Loop2 \r
+ mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
+\r
+Loop3 \r
+ orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
+ orr R0, R0, R7, LSL R2 ; factor in the index number\r
+\r
+ blx R1\r
+\r
+ subs R9, R9, #1 ; decrement the way number\r
+ bge Loop3\r
+ subs R7, R7, #1 ; decrement the index\r
+ bge Loop2\r
+Skip \r
+ add R10, R10, #2 ; increment the cache number\r
+ cmp R3, R10\r
+ bgt Loop1\r
+ \r
+Finished\r
+ dsb\r
+ ldmfd SP!, {r4-r12, lr}\r
+ bx LR\r
+\r
+ArmDataMemoryBarrier\r
+ dmb\r
+ bx LR\r
+ \r
+ArmDataSyncronizationBarrier\r
+ArmDrainWriteBuffer\r
+ dsb\r
+ bx LR\r
+ \r
+ArmInstructionSynchronizationBarrier\r
+ isb\r
+ bx LR\r
+\r
+ArmWriteVBar\r
+ // Set the Address of the Vector Table in the VBAR register\r
+ mcr p15, 0, r0, c12, c0, 0 \r
+ // Ensure the SCTLR.V bit is clear\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx lr\r
+\r
+ArmEnableVFP\r
+ // Read CPACR (Coprocessor Access Control Register)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
+ orr r0, r0, #0x00f00000\r
+ // Write back CPACR (Coprocessor Access Control Register)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
+ mov r0, #0x40000000\r
+ mcr p10,#0x7,r0,c8,c0,#0\r
+ bx lr\r
+\r
+ArmCallWFI\r
+ wfi\r
+ bx lr\r
+\r
+//Note: Return 0 in Uniprocessor implementation\r
+ArmReadCbar\r
+ mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
+ bx lr\r
+\r
+ArmInvalidateInstructionAndDataTlb\r
+ mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB\r
+ dsb\r
+ bx lr\r
+\r
+ArmReadMpidr\r
+ mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
+ bx lr\r
+\r
+ArmReadTpidrurw\r
+ mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
+ bx lr\r
+\r
+ArmWriteTpidrurw\r
+ mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
+ bx lr\r
+\r
+ArmIsArchTimerImplemented\r
+ mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
+ and r0, r0, #0x000F0000\r
+ bx lr\r
+\r
+ArmReadIdPfr1\r
+ mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
+ bx lr\r
+\r
+ END\r
projects / mirror_edk2.git / blobdiff