ArmPkg/ArmBaseLib: clean up directory structure

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / AArch64 / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
deleted file mode 100644 (file)
index 9d3dd66..0000000
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ /dev/null
@@ -1,190 +0,0 @@
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
-# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-\r
-.set DAIF_RD_FIQ_BIT,   (1 << 6)\r
-.set DAIF_RD_IRQ_BIT,   (1 << 7)\r
-\r
-ASM_FUNC(ArmReadMidr)\r
-  mrs     x0, midr_el1        // Read from Main ID Register (MIDR)\r
-  ret\r
-\r
-ASM_FUNC(ArmCacheInfo)\r
-  mrs     x0, ctr_el0         // Read from Cache Type Regiter (CTR)\r
-  ret\r
-\r
-ASM_FUNC(ArmGetInterruptState)\r
-  mrs     x0, daif\r
-  tst     w0, #DAIF_RD_IRQ_BIT  // Check if IRQ is enabled. Enabled if 0 (Z=1)\r
-  cset    w0, eq                // if Z=1 return 1, else 0\r
-  ret\r
-\r
-ASM_FUNC(ArmGetFiqState)\r
-  mrs     x0, daif\r
-  tst     w0, #DAIF_RD_FIQ_BIT  // Check if FIQ is enabled. Enabled if 0 (Z=1)\r
-  cset    w0, eq                // if Z=1 return 1, else 0\r
-  ret\r
-\r
-ASM_FUNC(ArmWriteCpacr)\r
-  msr     cpacr_el1, x0      // Coprocessor Access Control Reg (CPACR)\r
-  ret\r
-\r
-ASM_FUNC(ArmWriteAuxCr)\r
-  EL1_OR_EL2(x1)\r
-1:msr     actlr_el1, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
-  ret\r
-2:msr     actlr_el2, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
-  ret\r
-\r
-ASM_FUNC(ArmReadAuxCr)\r
-  EL1_OR_EL2(x1)\r
-1:mrs     x0, actlr_el1      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
-  ret\r
-2:mrs     x0, actlr_el2      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
-  ret\r
-\r
-ASM_FUNC(ArmSetTTBR0)\r
-  EL1_OR_EL2_OR_EL3(x1)\r
-1:msr     ttbr0_el1, x0      // Translation Table Base Reg 0 (TTBR0)\r
-  b       4f\r
-2:msr     ttbr0_el2, x0      // Translation Table Base Reg 0 (TTBR0)\r
-  b       4f\r
-3:msr     ttbr0_el3, x0      // Translation Table Base Reg 0 (TTBR0)\r
-4:isb\r
-  ret\r
-\r
-ASM_FUNC(ArmGetTTBR0BaseAddress)\r
-  EL1_OR_EL2(x1)\r
-1:mrs     x0, ttbr0_el1\r
-  b       3f\r
-2:mrs     x0, ttbr0_el2\r
-3:and     x0, x0, 0xFFFFFFFFFFFF  /* Look at bottom 48 bits */\r
-  isb\r
-  ret\r
-\r
-ASM_FUNC(ArmGetTCR)\r
-  EL1_OR_EL2_OR_EL3(x1)\r
-1:mrs     x0, tcr_el1\r
-  b       4f\r
-2:mrs     x0, tcr_el2\r
-  b       4f\r
-3:mrs     x0, tcr_el3\r
-4:isb\r
-  ret\r
-\r
-ASM_FUNC(ArmSetTCR)\r
-  EL1_OR_EL2_OR_EL3(x1)\r
-1:msr     tcr_el1, x0\r
-  b       4f\r
-2:msr     tcr_el2, x0\r
-  b       4f\r
-3:msr     tcr_el3, x0\r
-4:isb\r
-  ret\r
-\r
-ASM_FUNC(ArmGetMAIR)\r
-  EL1_OR_EL2_OR_EL3(x1)\r
-1:mrs     x0, mair_el1\r
-  b       4f\r
-2:mrs     x0, mair_el2\r
-  b       4f\r
-3:mrs     x0, mair_el3\r
-4:isb\r
-  ret\r
-\r
-ASM_FUNC(ArmSetMAIR)\r
-  EL1_OR_EL2_OR_EL3(x1)\r
-1:msr     mair_el1, x0\r
-  b       4f\r
-2:msr     mair_el2, x0\r
-  b       4f\r
-3:msr     mair_el3, x0\r
-4:isb\r
-  ret\r
-\r
-\r
-//\r
-//VOID\r
-//ArmUpdateTranslationTableEntry (\r
-//  IN VOID  *TranslationTableEntry  // X0\r
-//  IN VOID  *MVA                    // X1\r
-//  );\r
-ASM_FUNC(ArmUpdateTranslationTableEntry)\r
-   dc      civac, x0             // Clean and invalidate data line\r
-   dsb     sy\r
-   EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1\r
-   b       4f\r
-2: tlbi    vae2, x1              // TLB Invalidate VA , EL2\r
-   b       4f\r
-3: tlbi    vae3, x1              // TLB Invalidate VA , EL3\r
-4: dsb     sy\r
-   isb\r
-   ret\r
-\r
-ASM_FUNC(ArmInvalidateTlb)\r
-   EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi  vmalle1\r
-   b     4f\r
-2: tlbi  alle2\r
-   b     4f\r
-3: tlbi  alle3\r
-4: dsb   sy\r
-   isb\r
-   ret\r
-\r
-ASM_FUNC(ArmWriteCptr)\r
-  msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)\r
-  ret\r
-\r
-ASM_FUNC(ArmWriteScr)\r
-  msr     scr_el3, x0            // Secure configuration register EL3\r
-  isb\r
-  ret\r
-\r
-ASM_FUNC(ArmWriteMVBar)\r
-  msr    vbar_el3, x0            // Exception Vector Base address for Monitor on EL3\r
-  ret\r
-\r
-ASM_FUNC(ArmCallWFE)\r
-  wfe\r
-  ret\r
-\r
-ASM_FUNC(ArmCallSEV)\r
-  sev\r
-  ret\r
-\r
-ASM_FUNC(ArmReadCpuActlr)\r
-  mrs   x0, S3_1_c15_c2_0\r
-  ret\r
-\r
-ASM_FUNC(ArmWriteCpuActlr)\r
-  msr   S3_1_c15_c2_0, x0\r
-  dsb   sy\r
-  isb\r
-  ret\r
-\r
-ASM_FUNC(ArmReadSctlr)\r
-  EL1_OR_EL2_OR_EL3(x1)\r
-1:mrs   x0, sctlr_el1\r
-  ret\r
-2:mrs   x0, sctlr_el2\r
-  ret\r
-3:mrs   x0, sctlr_el3\r
-4:ret\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r